152 lines
5.0 KiB
Verilog
152 lines
5.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// Input must be RGB or CrYCb in that order, output is CrY/CbY
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module ad_ss_444to422 (
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// 444 inputs
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clk,
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s444_de,
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s444_sync,
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s444_data,
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// 422 outputs
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s422_sync,
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s422_data);
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// parameters
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parameter Cr_Cb_N = 0;
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parameter DELAY_DATA_WIDTH = 16;
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localparam DW = DELAY_DATA_WIDTH - 1;
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// 444 inputs
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input clk;
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input s444_de;
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input [DW:0] s444_sync;
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input [23:0] s444_data;
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// 422 outputs
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output [DW:0] s422_sync;
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output [15:0] s422_data;
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// internal registers
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reg s444_de_d = 'd0;
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reg [DW:0] s444_sync_d = 'd0;
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reg [23:0] s444_data_d = 'd0;
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reg s444_de_2d = 'd0;
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reg [DW:0] s444_sync_2d = 'd0;
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reg [23:0] s444_data_2d = 'd0;
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reg s444_de_3d = 'd0;
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reg [DW:0] s444_sync_3d = 'd0;
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reg [23:0] s444_data_3d = 'd0;
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reg [ 7:0] cr = 'd0;
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reg [ 7:0] cb = 'd0;
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reg cr_cb_sel = 'd0;
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reg [DW:0] s422_sync = 'd0;
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reg [15:0] s422_data = 'd0;
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// internal wires
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wire [ 9:0] cr_s;
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wire [ 9:0] cb_s;
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// fill the data pipe lines, hold the last data on edges
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always @(posedge clk) begin
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s444_de_d <= s444_de;
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s444_sync_d <= s444_sync;
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if (s444_de == 1'b1) begin
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s444_data_d <= s444_data;
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end
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s444_de_2d <= s444_de_d;
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s444_sync_2d <= s444_sync_d;
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if (s444_de_d == 1'b1) begin
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s444_data_2d <= s444_data_d;
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end
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s444_de_3d <= s444_de_2d;
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s444_sync_3d <= s444_sync_2d;
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if (s444_de_2d == 1'b1) begin
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s444_data_3d <= s444_data_2d;
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end
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end
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// get the average 0.25*s(n-1) + 0.5*s(n) + 0.25*s(n+1)
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assign cr_s = {2'd0, s444_data_d[23:16]} +
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{2'd0, s444_data_3d[23:16]} +
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{1'd0, s444_data_2d[23:16], 1'd0};
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assign cb_s = {2'd0, s444_data_d[7:0]} +
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{2'd0, s444_data_3d[7:0]} +
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{1'd0, s444_data_2d[7:0], 1'd0};
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always @(posedge clk) begin
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cr <= cr_s[9:2];
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cb <= cb_s[9:2];
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if (s444_de_3d == 1'b1) begin
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cr_cb_sel <= ~cr_cb_sel;
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end else begin
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cr_cb_sel <= Cr_Cb_N;
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end
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end
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// 422 outputs
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always @(posedge clk) begin
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s422_sync <= s444_sync_3d;
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if (s444_de_3d == 1'b0) begin
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s422_data <= 'd0;
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end else if (cr_cb_sel == 1'b1) begin
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s422_data <= {cr, s444_data_3d[15:8]};
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end else begin
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s422_data <= {cb, s444_data_3d[15:8]};
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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