69 lines
2.3 KiB
VHDL
69 lines
2.3 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- Each core or library found in this collection may have its own licensing terms.
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-- The user should keep this in in mind while exploring these cores.
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--
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-- Redistribution and use in source and binary forms,
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-- with or without modification of this file, are permitted under the terms of either
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-- (at the option of the user):
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory, or at:
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-- https:--www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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--
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-- OR
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--
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-- 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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-- https:--github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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library unisim;
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use unisim.all;
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entity util_i2c_mixer is
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generic (
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C_WIDTH: integer := 2
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);
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port (
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upstream_scl_T : in std_logic;
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upstream_scl_I : in std_logic;
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upstream_scl_O : out std_logic;
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upstream_sda_T : in std_logic;
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upstream_sda_I : in std_logic;
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upstream_sda_O : out std_logic;
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downstream_scl_T : out std_logic;
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downstream_scl_I : in std_logic_vector(C_WIDTH - 1 downto 0);
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downstream_scl_O : out std_logic_vector(C_WIDTH - 1 downto 0);
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downstream_sda_T : out std_logic;
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downstream_sda_I : in std_logic_vector(C_WIDTH - 1 downto 0);
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downstream_sda_O : out std_logic_vector(C_WIDTH - 1 downto 0)
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);
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end util_i2c_mixer;
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architecture IMP of util_i2c_mixer is
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begin
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upstream_scl_O <= '1' when (downstream_scl_I = (downstream_scl_I'range => '1')) else '0';
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upstream_sda_O <= '1' when (downstream_sda_I = (downstream_sda_I'range => '1')) else '0';
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downstream_scl_T <= upstream_scl_T;
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downstream_sda_T <= upstream_sda_T;
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GEN: for i in 0 to C_WIDTH - 1 generate
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downstream_scl_O(i) <= upstream_scl_I;
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downstream_sda_O(i) <= upstream_sda_I;
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end generate GEN;
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end IMP;
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