48 lines
1.8 KiB
Makefile
48 lines
1.8 KiB
Makefile
####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_adrv9009
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GENERIC_DEPS += ../common/ad_datafmt.v
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GENERIC_DEPS += ../common/ad_dds.v
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GENERIC_DEPS += ../common/ad_dds_1.v
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GENERIC_DEPS += ../common/ad_dds_sine.v
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GENERIC_DEPS += ../common/ad_iqcor.v
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/ad_xcvr_rx_if.v
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GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_dac_channel.v
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GENERIC_DEPS += ../common/up_dac_common.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_adrv9009.v
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GENERIC_DEPS += axi_adrv9009_if.v
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GENERIC_DEPS += axi_adrv9009_rx.v
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GENERIC_DEPS += axi_adrv9009_rx_channel.v
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GENERIC_DEPS += axi_adrv9009_rx_os.v
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GENERIC_DEPS += axi_adrv9009_tx.v
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GENERIC_DEPS += axi_adrv9009_tx_channel.v
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XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
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XILINX_DEPS += ../xilinx/common/ad_mul.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_adrv9009_ip.tcl
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ALTERA_DEPS += ../altera/common/ad_dcfilter.v
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ALTERA_DEPS += ../altera/common/ad_mul.v
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ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
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ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
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ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
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ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
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ALTERA_DEPS += axi_adrv9009_hw.tcl
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include ../scripts/library.mk
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