31 lines
1.4 KiB
Tcl
31 lines
1.4 KiB
Tcl
source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create util_clkdiv
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adi_ip_files util_clkdiv [list \
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"util_clkdiv_constr.xdc" \
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"util_clkdiv.v" ]
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adi_ip_properties_lite util_clkdiv
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set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \
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-of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]]
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set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
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set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
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set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]]
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set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
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set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]]
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set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
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set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]]
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adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \
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[list {"clk_out" "CLK"}]
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ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
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ipx::save_core [ipx::current_core]
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