46 lines
1.3 KiB
ReStructuredText
46 lines
1.3 KiB
ReStructuredText
.. _template_framework module:
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Template Module
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================================================================================
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.. hdl-component-diagram::
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:path: library/spi_engine/spi_engine_execution
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The {module name} is responsible for {brief description}.
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Files
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-------------------------------------------------------------------------------
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.. list-table::
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:widths: 25 75
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`library/spi_engine/spi_engine_execution/spi_engine_execution.v`
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- Verilog source for the peripheral.
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* - :git-hdl:`library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl`
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- TCL script to generate the Vivado IP-integrator project for the peripheral.
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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:path: library/spi_engine/spi_engine_interconnect
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* - DATA_WIDTH
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- Data width of the parallel SDI/SDO data interfaces.
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Signal and Interface Pins
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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:path: library/spi_engine/spi_engine_interconnect
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Theory of Operation
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--------------------------------------------------------------------------------
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The {module name} module implements {brief description}.
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.. image:: ../spi_engine/spi_engine.svg
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