317 lines
10 KiB
ReStructuredText
317 lines
10 KiB
ReStructuredText
.. _util_adxcvr:
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UTIL_ADXCVR core for AMD Xilinx devices
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================================================================================
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.. hdl-component-diagram::
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:path: library/xilinx/util_adxcvr
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The
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:git-hdl:`util_adxcvr <library/xilinx/util_adxcvr>`
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IP core instantiates a Gigabit Transceiver (GT) and sets up the required
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configuration. Basically, it is a simple wrapper file for a GT\* Column,
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exposing just the necessary ports and attributes.
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.. note::
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To understand the below wiki page is important to have a basic
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understanding about High Speed Serial I/O interfaces and Gigabit Serial
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Transceivers. To find more information about these technologies, please visit
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the :xilinx:`AMD Xilinx's solution center <support/answers/37181.html>`.
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Currently this IP supports three different GT types:
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- GTXE2
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(:xilinx:`7 Series devices <support/documentation/user_guides/ug476_7Series_Transceivers.pdf>`)
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- GTHE3
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(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`)
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- GTHE4
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(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`)
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- GTYE4
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(:xilinx:`Ultrascale and Ultrascale+ <support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf>`)
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Features
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--------------------------------------------------------------------------------
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* Supports GTX2, GTH3 and GTH4
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* Exposes all the necessary attributes for QPLL/CPLL configuration
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* Supports shared transceiver mode
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* Supports dynamic reconfiguration
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* RX Eye Scan
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Block Diagram
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--------------------------------------------------------------------------------
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The following diagram shows a GTXE2 Column, which contains four GT Quads. Each
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quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitives.
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.. image:: gtx_column.svg
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:align: center
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Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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* - XCVR_TYPE
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- | Define the current GT type:
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| GTXE2(0), GTHE3(1), GTHE4(2)
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* - QPLL_REFCLK_DIV
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- QPLL reference clock divider M, see User Guide for more info
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* - QPLL_FBDIV_RATIO
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- QPLL reference clock divider N ratio, see User Guide for more info
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* - QPLL_CFG
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- Configuration settings for QPLL, see User Guide for more info
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* - QPLL_FBDIV
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- QPLL reference clock divider N, see User Guide for more info
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* - CPLL_FBDIV
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- CPLL feedback divider N2 settings, see User Guide for more info
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* - CPLL_FBDIV_4_5
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- CPLL reference clock divider N1 settings, see User Guide for more info
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* - TX_NUM_OF_LANES
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- Number of transmit lanes.
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* - TX_OUT_DIV
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- CPLL/QPLL output clock divider D for the TX datapath, see User Guide for
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more info
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* - TX_CLK25_DIV
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- Divider for internal 25 MHz clock for the TX datapath, see User Guide
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for more info
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* - TX_LANE_INVERT
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- Per lane polarity inversion. Set the n-th bit to invert the polarity of
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the n-th transmit lane.
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* - RX_NUM_OF_LANES
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- Number of transmit lanes
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* - RX_OUT_DIV
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- CPLL/QPLL output clock divider D for the RX datapath, see User Guide for
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more info
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* - RX_CLK25_DIV
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- Divider for internal 25 MHz clock for the RX datapath, see User Guide
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for more info
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* - RX_DFE_LPM_CFG
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- Configure the GT use modes, LPM or DFE, see User Guide for more info
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* - RX_PMA_CFG
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- Search for PMA_RSV in User Guide for more info
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* - RX_CDR_CFG
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- Configure the RX clock data recovery circuit for GTXE2, see User Guide
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for more info
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* - RX_LANE_INVERT
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- Per lane polarity inversion. Set the n-th bit to invert the polarity of
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the n-th receive lane.
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Interface
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--------------------------------------------------------------------------------
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Microprocessor clock and reset
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - Pin
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- Type
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- Description
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* - ``up_clk``
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- ``input``
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- System clock, running on 100 MHz
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* - ``up_rstn``
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- ``input``
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- System reset, the same as AXI memory map slave interface reset
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PLL reference clock
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - Pin
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- Type
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- Description
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* - ``qpll_ref_clk_0``
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- ``input``
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- Reference clock for the QPLL
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* - ``cpll_ref_clk_0``
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- ``input``
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- Reference clock for the CPLL
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RX interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - Pin
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- Type
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- Description
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* - ``rx_*_p``
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- ``input``
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- Positive differential serial data input
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* - ``rx_*_n``
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- ``input``
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- Negative differential serial data input
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* - ``rx_out_clk_*``
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- ``output``
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- Core logic clock output. Frequency = serial line rate/40
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* - ``rx_clk_*``
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- ``input``
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- Core logic clock loop-back input
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* - ``rx_charisk_*``
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- ``output[3:0]``
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- RX Char is K to the JESD204B IP
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* - ``rx_disperr_*``
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- ``output[3:0]``
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- RX disparity error to the JESD204B IP
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* - ``rx_notintable_*``
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- ``output[3:0]``
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- RX Not In Table to the JESD204B IP
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* - ``rx_data_*``
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- ``output[3:0]``
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- RX data to the JESD204B IP
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* - ``rx_calign_*``
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- ``input``
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- RX enable comma alignment from the JESD204B IP
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TX interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - Pin
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- Type
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- Description
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* - ``tx_*_p``
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- ``output``
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- Positive differential serial output
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* - ``tx_*_n``
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- ``output``
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- Negative differential serial output
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* - ``tx_out_clk_*``
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- ``output``
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- Core logic clock output. Frequency = serial line rate/40
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* - ``tx_clk_*``
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- ``input``
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- Core logic clock loop-back input
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* - ``tx_charisk_*``
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- ``input[3:0]``
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- TX Char is K from the JESD204B IP
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* - ``tx_data_*``
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- ``input[31:0]``
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- TX data from the JESD204B IP
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Common DRP Interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - Pin
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- Type
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- Description
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* - ``up_cm_*``
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- ``IO``
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- The common DRP interface, must be connected to the equivalent DRP ports
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of AXI_ADXCVR. This is a QUAD interface, shared by four transceiver
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lanes. This interface is available only if parameter QPLL_ENABLE is set
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to 0x1.
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Channel DRP Interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - Pin
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- Type
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- Description
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* - ``up_rx_*``
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- ``IO``
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- The RX channel DRP interface, must be connected to the equivalent DRP ports
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of AXI_ADXCVR. This is a channel interface, one per each RX transceiver
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lane.
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* - ``up_tx_*``
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- ``IO``
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- The TX channel DRP interface, must be connected to the equivalent DRP ports
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of AXI_ADXCVR. This is a channel interface, one per each TX transceiver
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lane.
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Eye Scan DRP Interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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.. list-table::
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:header-rows: 1
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* - Pin
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- Type
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- Description
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* - ``up_es_*``
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- ``IO``
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- The Eye-Scan DRP interface, must be connected to the equivalent DRP
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ports of UTIL_ADXCVR. This is a channel interface, one per each
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transceiver lane. This interface is available only if parameter
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TX_OR_RX_N is set to 0x0.
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Design Guidelines
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--------------------------------------------------------------------------------
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.. note::
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Please refer to :dokuwiki:`AMD Xilinx FPGAs Transceivers Wizard <resources/fpga/docs/xgt_wizard>`
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to generate the optimal parameters needed to configure the transceivers for
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your project.
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Physical constraints considerations
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--------------------------------------------------------------------------------
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The util_adxcvr allocates resources/quads (channels and common) sequentially.
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Meaning, if you have 8 lanes it will insert two quads, 4 channels and a common
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block for each quad.
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Channels within a quad are tightly coupled to the common block, the placement of
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the channel resources can be permuted within a quad and is affected by the
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constraint file with the restriction that rx\_<N>_p/n connect to tx\_<N>_p/n
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must connect to the same channel.
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Supposing we have the following pin constraints and connections to the
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util_adxcvr:
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.. image:: xcvr_mapping_example.svg
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:align: center
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So in this case we end up with a conflict during implementation:
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.. image:: xcvr_conflict.svg
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:align: center
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We have to ensure that in implementation the mapping is correct either by
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rearranging the Rx connections
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.. image:: xcvr_rx_rearrangement.svg
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:align: center
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or by rearranging the Tx connections of the util_adxcvr:
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.. image:: xcvr_tx_rearrangement.svg
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:align: center
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In such cases, when rearrangement is required due placement constraints,
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complementary reordering is required either in the converter device (lane
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crossbars) or inside the FPGA between the physical and link layer, to connect
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the logical lanes with the same index on both end of the link.
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Software Guidelines
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--------------------------------------------------------------------------------
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The software can configure this core through the :ref:`AXI_ADXCVR <axi_adxcvr>` IP
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core.
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References
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- :xilinx:`High Speed Serial <products/technology/high-speed-serial.html>`
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- :xilinx:`7 Series FPGAs GTX/GTH Transceivers <support/documentation/user_guides/ug476_7Series_Transceivers.pdf>`
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- :xilinx:`UltraScale Architecture GTH Transceivers <support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf>`
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- :xilinx:`UltraScale Architecture GTY Transceivers <support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf>`
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More Information
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--------------------------------------------------------------------------------
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- :ref:`JESD204B High-Speed Serial Interface Support <jesd204>`
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