57 lines
1.5 KiB
Verilog
57 lines
1.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_scrambler #(
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parameter WIDTH = 32,
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parameter DESCRAMBLE = 0
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) (
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input clk,
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input reset,
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input enable,
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input [WIDTH-1:0] data_in,
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output [WIDTH-1:0] data_out
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);
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reg [14:0] state = 'h7f80;
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reg [WIDTH-1:0] swizzle_out;
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wire [WIDTH-1:0] swizzle_in;
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wire [WIDTH-1:0] feedback;
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wire [WIDTH-1+15:0] full_state;
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generate
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genvar i;
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for (i = 0; i < WIDTH / 8; i = i + 1) begin: gen_swizzle
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assign swizzle_in[WIDTH-1-i*8:WIDTH-i*8-8] = data_in[i*8+7:i*8];
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assign data_out[WIDTH-1-i*8:WIDTH-i*8-8] = swizzle_out[i*8+7:i*8];
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end
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endgenerate
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assign full_state = {state,DESCRAMBLE ? swizzle_in : feedback};
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assign feedback = full_state[WIDTH-1+15:15] ^ full_state[WIDTH-1+14:14] ^ swizzle_in;
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always @(*) begin
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if (enable == 1'b0) begin
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swizzle_out = swizzle_in;
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end else begin
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swizzle_out = feedback;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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state <= 'h7f80;
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end else begin
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state <= full_state[14:0];
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end
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end
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endmodule
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