47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module jesd204_scrambler_64b #(
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parameter WIDTH = 64,
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parameter DESCRAMBLE = 0
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) (
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input clk,
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input reset,
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input enable,
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input [WIDTH-1:0] data_in,
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output reg [WIDTH-1:0] data_out
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);
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reg [57:0] state = {1'b1,57'b0};
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wire [WIDTH-1:0] feedback;
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wire [WIDTH-1+58:0] full_state;
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assign full_state = {state,DESCRAMBLE ? data_in : feedback};
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assign feedback = full_state[WIDTH-1+58:58] ^ full_state[WIDTH-1:39] ^ data_in;
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always @(*) begin
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if (enable == 1'b0) begin
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data_out = data_in;
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end else begin
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data_out = feedback;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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state <= {1'b1,57'b0};
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end else begin
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state <= full_state[57:0] ^ {full_state[38:0],19'b0};
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end
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end
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endmodule
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