84 lines
3.3 KiB
Verilog
84 lines
3.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_pad #(
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parameter NUM_OF_SAMPLES = 2,
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parameter IN_BITS_PER_SAMPLE = 16,
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parameter OUT_BITS_PER_SAMPLE = 16,
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parameter PADDING_TO_MSB_LSB_N = 0,
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parameter SIGN_EXTEND = 1
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) (
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input [NUM_OF_SAMPLES*IN_BITS_PER_SAMPLE-1:0] data_in,
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output reg [NUM_OF_SAMPLES*OUT_BITS_PER_SAMPLE-1:0] data_out
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);
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// Remove padding
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if (IN_BITS_PER_SAMPLE >= OUT_BITS_PER_SAMPLE) begin
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integer i;
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always @(*) begin
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for (i=0;i<NUM_OF_SAMPLES;i=i+1) begin
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if (PADDING_TO_MSB_LSB_N==1) begin
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data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
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data_in[i*IN_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE];
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end else begin
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data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
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data_in[((i+1)*IN_BITS_PER_SAMPLE)-1 -: OUT_BITS_PER_SAMPLE];
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end
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end
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end
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end
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// Add padding
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if (IN_BITS_PER_SAMPLE < OUT_BITS_PER_SAMPLE) begin
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integer i;
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always @(*) begin
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for (i=0;i<NUM_OF_SAMPLES;i=i+1) begin
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if (PADDING_TO_MSB_LSB_N==1) begin
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data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
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{{OUT_BITS_PER_SAMPLE-IN_BITS_PER_SAMPLE{data_in[(i+1)*IN_BITS_PER_SAMPLE-1]&SIGN_EXTEND[0]}},
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data_in[i*IN_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE]};
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end else begin
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data_out[i*OUT_BITS_PER_SAMPLE +: OUT_BITS_PER_SAMPLE] =
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{data_in[((i+1)*IN_BITS_PER_SAMPLE)-1 -: OUT_BITS_PER_SAMPLE],
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{OUT_BITS_PER_SAMPLE-IN_BITS_PER_SAMPLE{1'b0}}};
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end
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end
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end
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end
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endmodule
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