4b13274c55
Having a clock assigned manually to the clk output pin of the axi_ad9361 let the Vivado timing engine to not ignore the clock insertion delay when analyzing paths between clk_0 and the manually created clock that has the same source (clk_0), resulting in timing failure. |
||
|---|---|---|
| .. | ||
| common | ||
| zc702 | ||
| zc706 | ||
| zcu102 | ||
| Makefile | ||