610cc3affa
The debug register logic for the DMA take up a fair amount of resources. Disabling them frees up space in the FPGA and also helps a bit with power. Since those registers are mainly useful in development and not so much in production the change shouldn't have any visible external effects. It is possible to re-enable the debug registers by setting DEBUG_BUILD=1. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
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