234 lines
6.5 KiB
Verilog
234 lines
6.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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sys_125m_clk_p,
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sys_125m_clk_n,
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uart_sin,
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uart_sout,
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ddr4_act_n,
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ddr4_addr,
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ddr4_ba,
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ddr4_bg,
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ddr4_ck_p,
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ddr4_ck_n,
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ddr4_cke,
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ddr4_cs_n,
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ddr4_dm_n,
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ddr4_dq,
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ddr4_dqs_p,
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ddr4_dqs_n,
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ddr4_odt,
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ddr4_par,
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ddr4_reset_n,
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mdio_mdc,
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mdio_mdio,
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phy_rst_n,
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phy_rx_p,
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phy_rx_n,
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phy_tx_p,
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phy_tx_n,
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fan_pwm,
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gpio_led,
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gpio_sw,
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iic_rstn,
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iic_scl,
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iic_sda,
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hdmi_out_clk,
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hdmi_hsync,
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hdmi_vsync,
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hdmi_data_e,
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hdmi_data,
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spdif);
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input sys_125m_clk_p;
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input sys_125m_clk_n;
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input uart_sin;
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output uart_sout;
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output ddr4_act_n;
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output [16:0] ddr4_addr;
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output [ 1:0] ddr4_ba;
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output [ 0:0] ddr4_bg;
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output ddr4_ck_p;
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output ddr4_ck_n;
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output [ 0:0] ddr4_cke;
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output [ 0:0] ddr4_cs_n;
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inout [ 7:0] ddr4_dm_n;
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inout [63:0] ddr4_dq;
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inout [ 7:0] ddr4_dqs_p;
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inout [ 7:0] ddr4_dqs_n;
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output [ 0:0] ddr4_odt;
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output ddr4_par;
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output ddr4_reset_n;
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output mdio_mdc;
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inout mdio_mdio;
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output phy_rst_n;
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input phy_rx_p;
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input phy_rx_n;
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output phy_tx_p;
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output phy_tx_n;
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output fan_pwm;
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inout [ 7:0] gpio_led;
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inout [ 8:0] gpio_sw;
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output iic_rstn;
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inout iic_scl;
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inout iic_sda;
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output hdmi_out_clk;
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output hdmi_hsync;
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output hdmi_vsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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// internal registers
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reg [31:0] sys_reset_m = 'd0;
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reg sys_cpu_rst = 'd0;
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reg sys_cpu_rstn = 'd0;
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// internal signals
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wire mdm_reset;
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wire mig_reset;
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wire mig_ready;
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wire sys_cpu_clk;
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// default logic
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assign fan_pwm = 1'b1;
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// assign sys_reset_req = mdm_reset | mig_reset | ~mig_ready;
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// assign sys_reset_req = mdm_reset;
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assign sys_reset_req = 1'b0;
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always @(posedge sys_cpu_clk) begin
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if (sys_reset_req == 1'b1) begin
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sys_reset_m <= {32{1'b1}};
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end else begin
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sys_reset_m <= {sys_reset_m[30:0], 1'b0};
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end
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sys_cpu_rst <= sys_reset_m[31];
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sys_cpu_rstn <= ~sys_reset_m[31];
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end
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// instantiations
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system_wrapper i_system_wrapper (
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.c0_ddr4_act_n (ddr4_act_n),
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.c0_ddr4_adr (ddr4_addr),
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.c0_ddr4_ba (ddr4_ba),
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.c0_ddr4_bg (ddr4_bg),
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.c0_ddr4_ck_c (ddr4_ck_n),
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.c0_ddr4_ck_t (ddr4_ck_p),
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.c0_ddr4_cke (ddr4_cke),
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.c0_ddr4_cs_n (ddr4_cs_n),
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.c0_ddr4_dm_n (ddr4_dm_n),
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.c0_ddr4_dq (ddr4_dq),
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.c0_ddr4_dqs_c (ddr4_dqs_n),
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.c0_ddr4_dqs_t (ddr4_dqs_p),
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.c0_ddr4_odt (ddr4_odt),
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.c0_ddr4_par (ddr4_par),
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.c0_ddr4_reset_n (ddr4_reset_n),
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.gpio_lcd_tri_io (),
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.gpio_led_tri_io (gpio_led),
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.gpio_sw_tri_io (gpio_sw),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.iic_rstn (iic_rstn),
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.mdio_mdc (mdio_mdc),
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.mdio_mdio_io (mdio_mdio),
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.mdm_reset (mdm_reset),
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.mig_ready (mig_ready),
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.mig_reset (mig_reset),
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.phy_rst_n (phy_rst_n),
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.phy_sd (1'b1),
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.sgmii_rxn (phy_rx_n),
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.sgmii_rxp (phy_rx_p),
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.sgmii_txn (phy_tx_n),
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.sgmii_txp (phy_tx_p),
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.spdif (spdif),
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.sys_125m_clk_n (sys_125m_clk_n),
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.sys_125m_clk_p (sys_125m_clk_p),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_cpu_clk (sys_cpu_clk),
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.sys_cpu_rst (sys_cpu_rst),
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.sys_cpu_rstn (sys_cpu_rstn),
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.sys_rst (sys_rst),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout),
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.unc_int2 (1'b0),
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.unc_int3 (1'b0),
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.unc_int4 (1'b0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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