35 lines
1.7 KiB
Plaintext
35 lines
1.7 KiB
Plaintext
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create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
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create_clock -period "12.500 ns" -name n_clk_80m [get_ports {ref_clk}]
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create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
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create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
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#create_clock -period "80.000 ns" -name spi_clk [get_nets {system_bd:i_system_bd|system_bd_sys_spi:sys_spi|SCLK_reg}]
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derive_pll_clocks
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derive_clock_uncertainty
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set clk_100m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set clk_166m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set clk_125m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set clk_25m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set clk_2m5 [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
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set_false_path -from {sys_resetn} -to *
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set_false_path -from $clk_100m -to $clk_166m
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set_false_path -from $clk_100m -to $clk_rxlink
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set_false_path -from $clk_166m -to $clk_100m
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set_false_path -from $clk_166m -to $clk_rxlink
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set_false_path -from $clk_rxlink -to $clk_100m
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set_false_path -from $clk_rxlink -to $clk_166m
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set_false_path -from $clk_125m -to $clk_25m
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set_false_path -from $clk_125m -to $clk_2m5
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set_false_path -from $clk_25m -to $clk_125m
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set_false_path -from $clk_25m -to $clk_2m5
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set_false_path -from $clk_2m5 -to $clk_125m
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set_false_path -from $clk_2m5 -to $clk_25m
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