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Lars-Peter Clausen 61be003017 axi_i2s/axi_spdif: Create clock and reset interface for DMA bus 
This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2014-10-10 16:11:41 +03:00
library axi_i2s/axi_spdif: Create clock and reset interface for DMA bus 2014-10-10 16:11:41 +03:00
projects Revert "fmcomms2_udc: Initial check in" 2014-10-10 14:48:55 +03:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga