297 lines
10 KiB
Tcl
297 lines
10 KiB
Tcl
###################################################################################################
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###################################################################################################
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variable sys_zynq
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variable sys_addr_cntrl_space
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variable sys_cpu_interconnect_index
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variable sys_hp0_interconnect_index
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variable sys_hp1_interconnect_index
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variable sys_hp2_interconnect_index
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variable sys_hp3_interconnect_index
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variable sys_mem_interconnect_index
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variable sys_interrupts_n
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variable sys_interrupts_q
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###################################################################################################
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###################################################################################################
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set sys_cpu_interconnect_index 0
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set sys_hp0_interconnect_index -1
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set sys_hp1_interconnect_index -1
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set sys_hp2_interconnect_index -1
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set sys_hp3_interconnect_index -1
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set sys_mem_interconnect_index -1
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set sys_interrupts_n 0
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###################################################################################################
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###################################################################################################
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proc ad_connect_type {p_name} {
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set m_name ""
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if {$m_name eq ""} {set m_name [get_bd_nets -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_pins -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_ports -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_intf_nets -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_intf_pins -quiet $p_name]}
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if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
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return $m_name
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}
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proc ad_connect {p_name_1 p_name_2} {
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set m_name_1 [ad_connect_type $p_name_1]
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set m_name_2 [ad_connect_type $p_name_2]
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if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
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connect_bd_intf_net $m_name_1 $m_name_2
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return
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}
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if {[get_property CLASS $m_name_1] eq "bd_pin"} {
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connect_bd_net $m_name_1 $m_name_2
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return
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}
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if {[get_property CLASS $m_name_1] eq "bd_net"} {
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set m_source_1 [filter [get_bd_pins -of_objects [get_bd_nets $m_name_1]] -regexp "DIR == O"]
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connect_bd_net -net $m_name_1 $m_name_2 $m_source_1
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return
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}
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}
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###################################################################################################
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###################################################################################################
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proc ad_mem_hp0_interconnect {p_clk p_name} {
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global sys_zynq
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
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}
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proc ad_mem_hp1_interconnect {p_clk p_name} {
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global sys_zynq
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
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}
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proc ad_mem_hp2_interconnect {p_clk p_name} {
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global sys_zynq
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
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}
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proc ad_mem_hp3_interconnect {p_name p_clk} {
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global sys_zynq
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if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
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if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
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}
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###################################################################################################
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###################################################################################################
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proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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global sys_zynq
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global sys_ddr_addr_seg
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global sys_hp0_interconnect_index
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global sys_hp1_interconnect_index
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global sys_hp2_interconnect_index
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global sys_hp3_interconnect_index
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global sys_mem_interconnect_index
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set p_intf_name [lrange [split $p_name "/"] end end]
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set p_cell_name [lrange [split $p_name "/"] 0 0]
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set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_cell_name]] \
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-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"]
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if {$p_sel eq "MEM"} {
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set m_interconnect_index $sys_mem_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
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set m_addr_seg $sys_ddr_addr_seg
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}
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if {$p_sel eq "HP0"} {
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set m_interconnect_index $sys_hp0_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
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set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
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}
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if {$p_sel eq "HP1"} {
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set m_interconnect_index $sys_hp1_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
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set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
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}
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if {$p_sel eq "HP2"} {
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set m_interconnect_index $sys_hp2_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
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set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
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}
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if {$p_sel eq "HP3"} {
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set m_interconnect_index $sys_hp3_interconnect_index
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set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
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set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
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}
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set i_str "S$m_interconnect_index"
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if {$m_interconnect_index < 10} {
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set i_str "S0$m_interconnect_index"
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}
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set m_interconnect_index [expr $m_interconnect_index + 1]
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set_property CONFIG.NUM_MI 1 $m_interconnect_cell
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if {$m_interconnect_index == 0} {
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set_property CONFIG.NUM_SI 1 $m_interconnect_cell
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ad_connect sys_cpu_resetn $m_interconnect_cell/ARESETN
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ad_connect $p_clk $m_interconnect_cell/ACLK
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ad_connect sys_cpu_resetn $m_interconnect_cell/M00_ARESETN
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ad_connect $p_clk $m_interconnect_cell/M00_ACLK
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ad_connect $m_interconnect_cell/M00_AXI $p_name
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ad_connect $p_clk $p_intf_clock
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} else {
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set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
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ad_connect sys_cpu_resetn $m_interconnect_cell/${i_str}_ARESETN
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ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
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ad_connect $m_interconnect_cell/${i_str}_AXI $p_name
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ad_connect $p_clk $p_intf_clock
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assign_bd_address $m_addr_seg
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}
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if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
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if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
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}
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###################################################################################################
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###################################################################################################
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proc ad_cpu_interconnect {p_address p_name} {
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global sys_zynq
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global sys_addr_cntrl_space
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global sys_cpu_interconnect_index
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set i_str "M$sys_cpu_interconnect_index"
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if {$sys_cpu_interconnect_index < 10} {
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set i_str "M0$sys_cpu_interconnect_index"
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}
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if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 1)} {
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ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
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ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
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ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
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ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
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ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
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ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
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}
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if {($sys_cpu_interconnect_index == 0) && ($sys_zynq == 0)} {
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ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
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ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
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ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
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ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
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ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
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}
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set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
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set p_intf [filter [get_bd_intf_pins -of_objects [get_bd_cells $p_name]] \
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-regexp "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"]
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set p_intf_name [lrange [split $p_intf "/"] end end]
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set p_intf_clock [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \
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-regexp "CONFIG.ASSOCIATED_BUSIF == ${p_intf_name}"]
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set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
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set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
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ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
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ad_connect sys_cpu_clk ${p_intf_clock}
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ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
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ad_connect sys_cpu_resetn ${p_name}/${p_intf_reset}
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ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
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set p_seg [get_bd_addr_segs -of_objects [get_bd_cells $p_name]]
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set p_index 0
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foreach p_seg_name $p_seg {
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if {$p_index == 0} {
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set p_seg_range [get_property range $p_seg_name]
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create_bd_addr_seg -range $p_seg_range \
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-offset $p_address $sys_addr_cntrl_space \
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$p_seg_name "SEG_data_${p_name}"
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} else {
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assign_bd_address $p_seg_name
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}
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incr p_index
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}
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}
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###################################################################################################
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###################################################################################################
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proc ad_cpu_interrupt {p_index p_name} {
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global sys_interrupts_n
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global sys_interrupts_q
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set i_str "In$p_index"
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if {$p_index >= $sys_interrupts_n} {
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set sys_interrupts_n [expr $p_index + 1]
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set_property CONFIG.NUM_PORTS $sys_interrupts_n [get_bd_cells sys_concat_intc]
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}
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set sys_interrupts_q($p_index) $p_name
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set p_intr [filter [get_bd_pins -quiet -of_objects [get_bd_cells $p_name]] \
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-regexp "TYPE == intr"]
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connect_bd_net -net "${p_name}_intr" \
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[get_bd_pins sys_concat_intc/${i_str}] \
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[get_bd_pins ${p_intr}]
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}
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proc ad_cpu_interrupt_update {} {
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global sys_zynq
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global sys_interrupts_n
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global sys_interrupts_q
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if {$sys_zynq == 1} {
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connect_bd_net -net sys_cpu_interrupt \
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[get_bd_pins sys_concat_intc/dout] \
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[get_bd_pins sys_ps7/IRQ_F2P]
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} else {
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connect_bd_net -net sys_cpu_interrupt \
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[get_bd_pins sys_concat_intc/dout] \
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[get_bd_pins axi_intc/intr]
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}
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for {set p_index 0} {$p_index < $sys_interrupts_n} {incr p_index} {
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if {![info exists sys_interrupts_q($p_index)]} {
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set i_str "In$p_index"
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set o_str "unc_intr_$p_index"
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create_bd_port -dir I ${o_str}
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connect_bd_net -net ${o_str} \
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[get_bd_pins sys_concat_intc/${i_str}] \
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[get_bd_ports ${o_str}]
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}
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}
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}
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###################################################################################################
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###################################################################################################
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