pluto_hdl_adi/projects/adrv9371x/zcu102
Michael Hennerich 2e59a70cdd adrv9371: Increase FCLK2 to 200MHz to support max sampling rates
This fixes an issue seen when using 307.2 MSPS on the Observation RX.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2018-01-09 15:20:06 +01:00
..
Makefile [axi|avl]_dacfifo: Create a separate bypass module for altera/xilinx 2017-09-25 08:56:40 +01:00
system_bd.tcl adrv9371: Increase FCLK2 to 200MHz to support max sampling rates 2018-01-09 15:20:06 +01:00
system_constr.xdc adrv9371x_zcu102: Fix rx_div_clk constraint placement 2017-11-20 15:36:51 +00:00
system_project.tcl Require Vivado 2017.2.1 for all zcu102 projects 2017-11-20 15:36:51 +00:00
system_top.v adrv9371x_zcu102: Initial commit 2017-08-22 15:48:03 +03:00