142 lines
4.4 KiB
Verilog
142 lines
4.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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output enable,
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output txnrx,
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output gpio_resetb,
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output gpio_sync,
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output gpio_en_agc,
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output [ 3:0] gpio_ctl,
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input [ 7:0] gpio_status,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso);
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// internal signals
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wire [95:0] gpio_i;
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wire [95:0] gpio_o;
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wire [ 2:0] spi0_csn;
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// defaults
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assign gpio_resetb = gpio_o[46:46];
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assign gpio_sync = gpio_o[45:45];
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assign gpio_en_agc = gpio_o[44:44];
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assign gpio_ctl = gpio_o[43:40];
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assign gpio_bd_o = gpio_o[20:13];
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assign gpio_i[95:40] = gpio_o[95:40];
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assign gpio_i[39:32] = gpio_status;
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assign gpio_i[31:13] = gpio_o[31:13];
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assign gpio_i[12: 0] = gpio_bd_i;
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assign spi_csn = spi0_csn[0];
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// instantiations
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system_wrapper i_system_wrapper (
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.enable (enable),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.ps_intr_14 (1'b0),
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.ps_intr_15 (1'b0),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.spi0_csn (spi0_csn),
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.spi0_miso (spi_miso),
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.spi0_mosi (spi_mosi),
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.spi0_sclk (spi_clk),
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.spi1_csn (),
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.spi1_miso (1'b0),
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.spi1_mosi (),
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.spi1_sclk (),
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.tdd_sync_i (1'b0),
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.tdd_sync_o (),
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.tdd_sync_t (),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.txnrx (txnrx),
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.up_enable (gpio_o[47]),
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.up_txnrx (gpio_o[48]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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