124 lines
4.3 KiB
Verilog
124 lines
4.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_var_fifo #(
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parameter DATA_WIDTH = 32,
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parameter ADDRESS_WIDTH = 13) (
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input clk,
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input rst,
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input [31:0] depth,
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input [ -1:0] data_in,
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input data_in_valid,
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output [DATA_WIDTH-1:0] data_out,
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output data_out_valid
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);
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localparam MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1;
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// internal registers
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reg [ADDRESS_WIDTH-1:0] addra = 'd0;
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reg [ADDRESS_WIDTH-1:0] addrb = 'd0;
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reg [31:0] depth_d1 = 'd0;
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reg [31:0] data_in_d1 = 'd0;
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reg [31:0] data_in_d2 = 'd0;
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reg data_active = 'd0;
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// internal signals
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wire reset;
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wire [31:0] depth;
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wire [DATA_WIDTH-1:0] data_out_s;
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wire data_out_valid_s;
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assign reset = ((rst == 1'b1) || (depth != depth_d1)) ? 1 : 0;
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assign data_out = (depth == 0) ? data_in_d2 : data_out_s;
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assign data_out_valid_s = data_active & data_in_valid;
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assign data_out_valid = (depth == 0) ? data_in_valid : data_out_valid_s;
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always @(posedge clk) begin
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depth_d1 <= depth;
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data_in_d1 <= data_in;
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data_in_d2 <= data_in_d1;
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end
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always @(posedge clk) begin
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if(reset == 1'b1) begin
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addra <= 0;
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addrb <= 0;
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data_active <= 1'b0;
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end else begin
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if (data_in_valid == 1'b1) begin
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addra <= addra + 1;
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if (data_active == 1'b1) begin
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addrb <= addrb + 1;
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end
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end
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if (addra >= depth || addra > MAX_DEPTH - 2) begin
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data_active <= 1'b1;
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end
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end
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end
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ad_mem #(
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.DATA_WIDTH(DATA_WIDTH),
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.ADDRESS_WIDTH(ADDRESS_WIDTH)
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) data_fifo (
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.clka(clk),
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.wea(data_in_valid),
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.addra(addra),
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.dina(data_in),
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.clkb(clk),
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.addrb(addrb),
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.doutb(data_out_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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