457 lines
17 KiB
Verilog
Executable File
457 lines
17 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dmac_alt (
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awid,
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s_axi_awlen,
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s_axi_awsize,
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s_axi_awburst,
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s_axi_awlock,
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s_axi_awcache,
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s_axi_awprot,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wlast,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bid,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arid,
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s_axi_arlen,
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s_axi_arsize,
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s_axi_arburst,
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s_axi_arlock,
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s_axi_arcache,
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s_axi_arprot,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rid,
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s_axi_rlast,
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s_axi_rready,
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// axi master interface (destination)
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m_dest_axi_aclk,
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m_dest_axi_aresetn,
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m_dest_axi_awvalid,
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m_dest_axi_awaddr,
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m_dest_axi_awid,
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m_dest_axi_awlen,
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m_dest_axi_awsize,
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m_dest_axi_awburst,
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m_dest_axi_awlock,
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m_dest_axi_awcache,
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m_dest_axi_awprot,
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m_dest_axi_awready,
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m_dest_axi_wvalid,
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m_dest_axi_wdata,
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m_dest_axi_wstrb,
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m_dest_axi_wlast,
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m_dest_axi_wready,
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m_dest_axi_bvalid,
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m_dest_axi_bresp,
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m_dest_axi_bid,
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m_dest_axi_bready,
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m_dest_axi_arvalid,
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m_dest_axi_araddr,
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m_dest_axi_arid,
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m_dest_axi_arlen,
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m_dest_axi_arsize,
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m_dest_axi_arburst,
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m_dest_axi_arlock,
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m_dest_axi_arcache,
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m_dest_axi_arprot,
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m_dest_axi_arready,
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m_dest_axi_rvalid,
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m_dest_axi_rresp,
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m_dest_axi_rdata,
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m_dest_axi_rid,
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m_dest_axi_rlast,
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m_dest_axi_rready,
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// axi master interface (source)
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m_src_axi_aclk,
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m_src_axi_aresetn,
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m_src_axi_awvalid,
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m_src_axi_awaddr,
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m_src_axi_awid,
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m_src_axi_awlen,
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m_src_axi_awsize,
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m_src_axi_awburst,
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m_src_axi_awlock,
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m_src_axi_awcache,
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m_src_axi_awprot,
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m_src_axi_awready,
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m_src_axi_wvalid,
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m_src_axi_wdata,
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m_src_axi_wstrb,
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m_src_axi_wlast,
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m_src_axi_wready,
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m_src_axi_bvalid,
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m_src_axi_bresp,
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m_src_axi_bid,
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m_src_axi_bready,
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m_src_axi_arvalid,
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m_src_axi_araddr,
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m_src_axi_arid,
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m_src_axi_arlen,
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m_src_axi_arsize,
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m_src_axi_arburst,
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m_src_axi_arlock,
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m_src_axi_arcache,
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m_src_axi_arprot,
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m_src_axi_arready,
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m_src_axi_rvalid,
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m_src_axi_rresp,
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m_src_axi_rdata,
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m_src_axi_rid,
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m_src_axi_rlast,
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m_src_axi_rready,
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// axis
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s_axis_aclk,
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s_axis_ready,
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s_axis_valid,
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s_axis_data,
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s_axis_user,
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m_axis_aclk,
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m_axis_ready,
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m_axis_valid,
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m_axis_data,
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// fifo
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fifo_wr_clk,
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fifo_wr_en,
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fifo_wr_din,
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fifo_wr_overflow,
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fifo_wr_sync,
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fifo_rd_clk,
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fifo_rd_en,
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fifo_rd_valid,
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fifo_rd_dout,
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fifo_rd_underflow,
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irq);
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parameter PCORE_ID = 0;
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parameter PCORE_AXI_ID_WIDTH = 3;
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parameter C_DMA_DATA_WIDTH_SRC = 64;
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parameter C_DMA_DATA_WIDTH_DEST = 64;
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parameter C_DMA_LENGTH_WIDTH = 14;
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parameter C_2D_TRANSFER = 1;
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parameter C_CLKS_ASYNC_REQ_SRC = 1;
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parameter C_CLKS_ASYNC_SRC_DEST = 1;
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parameter C_CLKS_ASYNC_DEST_REQ = 1;
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parameter C_AXI_SLICE_DEST = 0;
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parameter C_AXI_SLICE_SRC = 0;
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parameter C_SYNC_TRANSFER_START = 0;
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parameter C_CYCLIC = 1;
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parameter C_DMA_TYPE_DEST = 0;
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parameter C_DMA_TYPE_SRC = 2;
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// axi slave interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [13:0] s_axi_awaddr;
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input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_awid;
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input [ 7:0] s_axi_awlen;
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input [ 2:0] s_axi_awsize;
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input [ 1:0] s_axi_awburst;
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input [ 0:0] s_axi_awlock;
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input [ 3:0] s_axi_awcache;
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input [ 2:0] s_axi_awprot;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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input s_axi_wlast;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_bid;
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input s_axi_bready;
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input s_axi_arvalid;
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input [13:0] s_axi_araddr;
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input [(PCORE_AXI_ID_WIDTH-1):0] s_axi_arid;
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input [ 7:0] s_axi_arlen;
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input [ 2:0] s_axi_arsize;
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input [ 1:0] s_axi_arburst;
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input [ 0:0] s_axi_arlock;
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input [ 3:0] s_axi_arcache;
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input [ 2:0] s_axi_arprot;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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output [(PCORE_AXI_ID_WIDTH-1):0] s_axi_rid;
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output s_axi_rlast;
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input s_axi_rready;
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// axi master interface (destination)
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input m_dest_axi_aclk;
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input m_dest_axi_aresetn;
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output m_dest_axi_awvalid;
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output [31:0] m_dest_axi_awaddr;
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output [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_awid;
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output [ 7:0] m_dest_axi_awlen;
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output [ 2:0] m_dest_axi_awsize;
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output [ 1:0] m_dest_axi_awburst;
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output [ 0:0] m_dest_axi_awlock;
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output [ 3:0] m_dest_axi_awcache;
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output [ 2:0] m_dest_axi_awprot;
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input m_dest_axi_awready;
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output m_dest_axi_wvalid;
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output [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata;
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output [(C_DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb;
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output m_dest_axi_wlast;
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input m_dest_axi_wready;
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input m_dest_axi_bvalid;
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input [ 1:0] m_dest_axi_bresp;
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input [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_bid;
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output m_dest_axi_bready;
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output m_dest_axi_arvalid;
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output [31:0] m_dest_axi_araddr;
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output [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_arid;
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output [ 7:0] m_dest_axi_arlen;
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output [ 2:0] m_dest_axi_arsize;
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output [ 1:0] m_dest_axi_arburst;
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output [ 0:0] m_dest_axi_arlock;
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output [ 3:0] m_dest_axi_arcache;
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output [ 2:0] m_dest_axi_arprot;
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input m_dest_axi_arready;
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input m_dest_axi_rvalid;
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input [ 1:0] m_dest_axi_rresp;
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input [C_DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata;
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input [(PCORE_AXI_ID_WIDTH-1):0] m_dest_axi_rid;
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input m_dest_axi_rlast;
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output m_dest_axi_rready;
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// axi master interface (source)
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input m_src_axi_aclk;
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input m_src_axi_aresetn;
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output m_src_axi_awvalid;
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output [31:0] m_src_axi_awaddr;
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output [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_awid;
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output [ 7:0] m_src_axi_awlen;
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output [ 2:0] m_src_axi_awsize;
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output [ 1:0] m_src_axi_awburst;
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output [ 0:0] m_src_axi_awlock;
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output [ 3:0] m_src_axi_awcache;
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output [ 2:0] m_src_axi_awprot;
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input m_src_axi_awready;
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output m_src_axi_wvalid;
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output [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata;
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output [(C_DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb;
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output m_src_axi_wlast;
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input m_src_axi_wready;
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input m_src_axi_bvalid;
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input [ 1:0] m_src_axi_bresp;
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input [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_bid;
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output m_src_axi_bready;
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output m_src_axi_arvalid;
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output [31:0] m_src_axi_araddr;
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output [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_arid;
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output [ 7:0] m_src_axi_arlen;
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output [ 2:0] m_src_axi_arsize;
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output [ 1:0] m_src_axi_arburst;
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output [ 0:0] m_src_axi_arlock;
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output [ 3:0] m_src_axi_arcache;
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output [ 2:0] m_src_axi_arprot;
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input m_src_axi_arready;
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input m_src_axi_rvalid;
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input [ 1:0] m_src_axi_rresp;
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input [C_DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata;
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input [(PCORE_AXI_ID_WIDTH-1):0] m_src_axi_rid;
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input m_src_axi_rlast;
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output m_src_axi_rready;
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// axis
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input s_axis_aclk;
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output s_axis_ready;
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input s_axis_valid;
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input [C_DMA_DATA_WIDTH_SRC-1:0] s_axis_data;
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input [ 0:0] s_axis_user;
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input m_axis_aclk;
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input m_axis_ready;
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output m_axis_valid;
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output [C_DMA_DATA_WIDTH_DEST-1:0] m_axis_data;
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// fifo
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input fifo_wr_clk;
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input fifo_wr_en;
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input [C_DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din;
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output fifo_wr_overflow;
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input fifo_wr_sync;
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input fifo_rd_clk;
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input fifo_rd_en;
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output fifo_rd_valid;
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output [C_DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout;
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output fifo_rd_underflow;
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output irq;
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// defaults
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assign s_axi_bid = 'd0;
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assign s_axi_rid = 'd0;
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assign s_axi_rlast = 1'd0;
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// instantiation
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axi_dmac #(
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.PCORE_ID (PCORE_ID),
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.C_BASEADDR (32'h00000000),
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.C_HIGHADDR (32'hffffffff),
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.C_DMA_DATA_WIDTH_SRC (C_DMA_DATA_WIDTH_SRC),
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.C_DMA_DATA_WIDTH_DEST (C_DMA_DATA_WIDTH_DEST),
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.C_DMA_LENGTH_WIDTH (C_DMA_LENGTH_WIDTH),
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.C_2D_TRANSFER (C_2D_TRANSFER),
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.C_CLKS_ASYNC_REQ_SRC (C_CLKS_ASYNC_REQ_SRC),
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.C_CLKS_ASYNC_SRC_DEST (C_CLKS_ASYNC_SRC_DEST),
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.C_CLKS_ASYNC_DEST_REQ (C_CLKS_ASYNC_DEST_REQ),
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.C_AXI_SLICE_DEST (C_AXI_SLICE_DEST),
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.C_AXI_SLICE_SRC (C_AXI_SLICE_SRC),
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.C_SYNC_TRANSFER_START (C_SYNC_TRANSFER_START),
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.C_CYCLIC (C_CYCLIC),
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.C_DMA_TYPE_DEST (C_DMA_TYPE_DEST),
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.C_DMA_TYPE_SRC (C_DMA_TYPE_SRC))
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i_axi_dmac (
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awaddr ({18'd0, s_axi_awaddr}),
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.s_axi_awready (s_axi_awready),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wready (s_axi_wready),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bready (s_axi_bready),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_araddr ({18'd0, s_axi_araddr}),
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.s_axi_arready (s_axi_arready),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rdata (s_axi_rdata),
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.irq (irq),
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.m_dest_axi_aclk (m_dest_axi_aclk),
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.m_dest_axi_aresetn (m_dest_axi_aresetn),
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.m_src_axi_aclk (m_src_axi_aclk),
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.m_src_axi_aresetn (m_src_axi_aresetn),
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.m_dest_axi_awaddr (m_dest_axi_awaddr),
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.m_dest_axi_awlen (m_dest_axi_awlen),
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.m_dest_axi_awsize (m_dest_axi_awsize),
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.m_dest_axi_awburst (m_dest_axi_awburst),
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.m_dest_axi_awprot (m_dest_axi_awprot),
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.m_dest_axi_awcache (m_dest_axi_awcache),
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.m_dest_axi_awvalid (m_dest_axi_awvalid),
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.m_dest_axi_awready (m_dest_axi_awready),
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.m_dest_axi_wdata (m_dest_axi_wdata),
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.m_dest_axi_wstrb (m_dest_axi_wstrb),
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.m_dest_axi_wready (m_dest_axi_wready),
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.m_dest_axi_wvalid (m_dest_axi_wvalid),
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.m_dest_axi_wlast (m_dest_axi_wlast),
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.m_dest_axi_bvalid (m_dest_axi_bvalid),
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.m_dest_axi_bresp (m_dest_axi_bresp),
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.m_dest_axi_bready (m_dest_axi_bready),
|
|
.m_src_axi_arready (m_src_axi_arready),
|
|
.m_src_axi_arvalid (m_src_axi_arvalid),
|
|
.m_src_axi_araddr (m_src_axi_araddr),
|
|
.m_src_axi_arlen (m_src_axi_arlen),
|
|
.m_src_axi_arsize (m_src_axi_arsize),
|
|
.m_src_axi_arburst (m_src_axi_arburst),
|
|
.m_src_axi_arprot (m_src_axi_arprot),
|
|
.m_src_axi_arcache (m_src_axi_arcache),
|
|
.m_src_axi_rdata (m_src_axi_rdata),
|
|
.m_src_axi_rready (m_src_axi_rready),
|
|
.m_src_axi_rvalid (m_src_axi_rvalid),
|
|
.m_src_axi_rresp (m_src_axi_rresp),
|
|
.s_axis_aclk (s_axis_aclk),
|
|
.s_axis_ready (s_axis_ready),
|
|
.s_axis_valid (s_axis_valid),
|
|
.s_axis_data (s_axis_data),
|
|
.s_axis_user (s_axis_user),
|
|
.m_axis_aclk (m_axis_aclk),
|
|
.m_axis_ready (m_axis_ready),
|
|
.m_axis_valid (m_axis_valid),
|
|
.m_axis_data (m_axis_data),
|
|
.fifo_wr_clk (fifo_wr_clk),
|
|
.fifo_wr_en (fifo_wr_en),
|
|
.fifo_wr_din (fifo_wr_din),
|
|
.fifo_wr_overflow (fifo_wr_overflow),
|
|
.fifo_wr_sync (fifo_wr_sync),
|
|
.fifo_rd_clk (fifo_rd_clk),
|
|
.fifo_rd_en (fifo_rd_en),
|
|
.fifo_rd_valid (fifo_rd_valid),
|
|
.fifo_rd_dout (fifo_rd_dout),
|
|
.fifo_rd_underflow (fifo_rd_underflow));
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|
|
|
endmodule
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// ***************************************************************************
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// ***************************************************************************
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