zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
2,405 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Adrian Costina 667e49fe41 library: Axi_clkgen, added register for controlling the source clock. 
Address is 0x11 /0x44.
With the default value, 0, clock 1 is selected. If set to 1, clock 2 is selected
 		2015-11-25 11:16:32 +02:00
library library: Axi_clkgen, added register for controlling the source clock. 2015-11-25 11:16:32 +02:00
projects daq2: A10GX, add project specific IP search paths 2015-11-25 10:58:36 +02:00
.gitattributes Add .gitattributes file 2015-06-26 11:07:10 +02:00
.gitignore ignore gui 2015-09-22 16:32:02 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update Vivado's version number 2015-09-29 15:11:10 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.