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Lars-Peter Clausen 669a2da735 common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion 
Both the sys_hps.f2sdram_clock and the sys_dma_clk.clk signal are in the
same clock domain. They are both driven by the same clock. And even though
qsys is capable of detecting this it seems qsys interconnect is not able to
infer this and inserts a extra clock domain crossing bridge between the DMA
and the HPS AXI system memory interface.

To avoid this connect the sys_dma_clk.clk to the sys_hps.f2sdram_clock so
that all components are driven by the same qsys clock signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-07-20 19:45:27 +02:00
library up_clock_mon: Explicitly truncate d_count during up_d_count assignment 2017-07-20 19:45:27 +02:00
projects common: a10soc: Avoid unnecessary DMA clock domain crossing bridge insertion 2017-07-20 19:45:27 +02:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE license: GPL must be GPL v2 2017-05-31 18:18:45 +03:00
LICENSE_ADIBSD license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_GPL2 license: Add top level license files 2017-05-29 09:57:39 +03:00
LICENSE_LGPL license: Add top level license files 2017-05-29 09:57:39 +03:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

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