554 lines
17 KiB
Verilog
554 lines
17 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adxcvr_es (
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// up interface
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input up_rstn,
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input up_clk,
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output up_es_enb,
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output [11:0] up_es_addr,
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output up_es_wr,
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output [15:0] up_es_wdata,
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input [15:0] up_es_rdata,
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input up_es_ready,
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input up_ch_lpm_dfe_n,
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input up_es_req,
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output up_es_ack,
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input [ 4:0] up_es_pscale,
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input [ 1:0] up_es_vrange,
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input [ 7:0] up_es_vstep,
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input [ 7:0] up_es_vmax,
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input [ 7:0] up_es_vmin,
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input [11:0] up_es_hmax,
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input [11:0] up_es_hmin,
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input [11:0] up_es_hstep,
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input [31:0] up_es_saddr,
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output up_es_status,
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// axi interface
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output up_axi_awvalid,
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output [31:0] up_axi_awaddr,
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output [ 2:0] up_axi_awprot,
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input up_axi_awready,
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output up_axi_wvalid,
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output [31:0] up_axi_wdata,
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output [ 3:0] up_axi_wstrb,
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input up_axi_wready,
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input up_axi_bvalid,
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input [ 1:0] up_axi_bresp,
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output up_axi_bready,
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output up_axi_arvalid,
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output [31:0] up_axi_araddr,
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output [ 2:0] up_axi_arprot,
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input up_axi_arready,
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input up_axi_rvalid,
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input [31:0] up_axi_rdata,
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input [ 1:0] up_axi_rresp,
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output up_axi_rready);
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// parameters
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parameter integer GTH_OR_GTX_N = 0;
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parameter integer TX_OR_RX_N = 0;
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// addresses
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localparam [11:0] ES_DRP_CTRL_ADDR = (GTH_OR_GTX_N == 1) ? 12'h03c : 12'h03d; // GTH-7 12'h03d
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localparam [11:0] ES_DRP_HOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h04f : 12'h03c; // GTH-7 12'h03c
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localparam [11:0] ES_DRP_VOFFSET_ADDR = (GTH_OR_GTX_N == 1) ? 12'h097 : 12'h03b; // GTH-7 12'h03b
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localparam [11:0] ES_DRP_STATUS_ADDR = (GTH_OR_GTX_N == 1) ? 12'h153 : 12'h151; // GTH-7 12'h153
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localparam [11:0] ES_DRP_SCNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h152 : 12'h150; // GTH-7 12'h152
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localparam [11:0] ES_DRP_ECNT_ADDR = (GTH_OR_GTX_N == 1) ? 12'h151 : 12'h14f; // GTH-7 12'h151
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// fsm-states
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localparam [ 4:0] ES_FSM_IDLE = 6'h00;
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localparam [ 4:0] ES_FSM_HOFFSET_READ = 6'h01;
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localparam [ 4:0] ES_FSM_HOFFSET_RRDY = 6'h02;
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localparam [ 4:0] ES_FSM_HOFFSET_WRITE = 6'h03;
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localparam [ 4:0] ES_FSM_HOFFSET_WRDY = 6'h04;
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localparam [ 4:0] ES_FSM_VOFFSET_READ = 6'h05;
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localparam [ 4:0] ES_FSM_VOFFSET_RRDY = 6'h06;
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localparam [ 4:0] ES_FSM_VOFFSET_WRITE = 6'h07;
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localparam [ 4:0] ES_FSM_VOFFSET_WRDY = 6'h08;
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localparam [ 4:0] ES_FSM_CTRL_READ = 6'h09;
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localparam [ 4:0] ES_FSM_CTRL_RRDY = 6'h0a;
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localparam [ 4:0] ES_FSM_START_WRITE = 6'h0b;
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localparam [ 4:0] ES_FSM_START_WRDY = 6'h0c;
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localparam [ 4:0] ES_FSM_STATUS_READ = 6'h0d;
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localparam [ 4:0] ES_FSM_STATUS_RRDY = 6'h0e;
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localparam [ 4:0] ES_FSM_STOP_WRITE = 6'h0f;
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localparam [ 4:0] ES_FSM_STOP_WRDY = 6'h10;
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localparam [ 4:0] ES_FSM_SCNT_READ = 6'h11;
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localparam [ 4:0] ES_FSM_SCNT_RRDY = 6'h12;
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localparam [ 4:0] ES_FSM_ECNT_READ = 6'h13;
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localparam [ 4:0] ES_FSM_ECNT_RRDY = 6'h14;
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localparam [ 4:0] ES_FSM_AXI_WRITE = 6'h15;
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localparam [ 4:0] ES_FSM_AXI_READY = 6'h16;
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localparam [ 4:0] ES_FSM_UPDATE = 6'h17;
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// internal registers
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reg up_awvalid = 'd0;
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reg [31:0] up_awaddr = 'd0;
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reg up_wvalid = 'd0;
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reg [31:0] up_wdata = 'd0;
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reg up_status = 'd0;
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reg up_ut = 'd0;
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reg [31:0] up_daddr = 'd0;
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reg [11:0] up_hindex = 'd0;
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reg [ 7:0] up_vindex = 'd0;
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reg [15:0] up_hdata = 'd0;
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reg [15:0] up_vdata = 'd0;
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reg [15:0] up_cdata = 'd0;
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reg [15:0] up_sdata = 'd0;
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reg [15:0] up_edata = 'd0;
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reg up_req_d = 'd0;
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reg up_ack = 'd0;
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reg [ 4:0] up_fsm = 'd0;
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reg up_enb = 'd0;
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reg [11:0] up_addr = 'd0;
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reg up_wr = 'd0;
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reg [15:0] up_data = 'd0;
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// internal signals
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wire up_heos_s;
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wire up_eos_s;
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wire up_ut_s;
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wire [ 7:0] up_vindex_m_s;
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wire [ 7:0] up_vindex_n_s;
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wire [ 7:0] up_vindex_s;
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wire up_start_s;
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// axi interface
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generate
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if (TX_OR_RX_N == 1) begin
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assign up_axi_awvalid = 1'b0;
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assign up_axi_awaddr = 32'd0;
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assign up_axi_awprot = 3'd0;
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assign up_axi_wvalid = 1'b0;
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assign up_axi_wdata = 32'd0;
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assign up_axi_wstrb = 4'hf;
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assign up_axi_bready = 1'b1;
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assign up_axi_arvalid = 1'b0;
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assign up_axi_araddr = 32'd0;
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assign up_axi_arprot = 3'd0;
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assign up_axi_rready = 1'b1;
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end else begin
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assign up_axi_awvalid = up_awvalid;
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assign up_axi_awaddr = up_awaddr;
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assign up_axi_awprot = 3'd0;
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assign up_axi_wvalid = up_wvalid;
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assign up_axi_wdata = up_wdata;
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assign up_axi_wstrb = 4'hf;
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assign up_axi_bready = 1'b1;
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assign up_axi_arvalid = 1'b0;
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assign up_axi_araddr = 32'd0;
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assign up_axi_arprot = 3'd0;
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assign up_axi_rready = 1'b1;
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end
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endgenerate
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// reconfig interface
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generate
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if (TX_OR_RX_N == 1) begin
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assign up_es_ack = 1'b1;
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assign up_es_enb = 1'b0;
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assign up_es_addr = 12'd0;
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assign up_es_wr = 1'd0;
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assign up_es_wdata = 16'd0;
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assign up_es_status = 1'd0;
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end else begin
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assign up_es_ack = up_ack;
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assign up_es_enb = up_enb;
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assign up_es_addr = up_addr;
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assign up_es_wr = up_wr;
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assign up_es_wdata = up_data;
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assign up_es_status = up_status;
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end
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endgenerate
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// axi write
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_awvalid <= 'b0;
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up_awaddr <= 'd0;
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up_wvalid <= 'b0;
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up_wdata <= 'd0;
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up_status <= 'd0;
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end else begin
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if ((up_awvalid == 1'b1) && (up_axi_awready == 1'b1)) begin
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up_awvalid <= 1'b0;
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up_awaddr <= 32'd0;
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end else if (up_fsm == ES_FSM_AXI_WRITE) begin
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up_awvalid <= 1'b1;
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up_awaddr <= up_daddr;
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end
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if ((up_wvalid == 1'b1) && (up_axi_wready == 1'b1)) begin
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up_wvalid <= 1'b0;
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up_wdata <= 32'd0;
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end else if (up_fsm == ES_FSM_AXI_WRITE) begin
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up_wvalid <= 1'b1;
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up_wdata <= {up_sdata, up_edata};
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end
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if (up_axi_bvalid == 1'b1) begin
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up_status <= | up_axi_bresp;
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end
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end
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end
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// prescale, horizontal and vertical offsets
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assign up_heos_s = (up_hindex == up_es_hmax) ? up_ut : 1'b0;
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assign up_eos_s = (up_vindex == up_es_vmax) ? up_heos_s : 1'b0;
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assign up_ut_s = up_ut & ~up_ch_lpm_dfe_n;
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assign up_vindex_m_s = ~up_vindex + 1'b1;
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assign up_vindex_n_s = {1'b1, up_vindex_m_s[6:0]};
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assign up_vindex_s = (up_vindex[7] == 1'b1) ? up_vindex_n_s : up_vindex;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_ut <= 'd0;
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up_daddr <= 'd0;
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up_hindex <= 'd0;
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up_vindex <= 'd0;
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end else begin
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if (up_fsm == ES_FSM_IDLE) begin
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up_ut <= up_ch_lpm_dfe_n;
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up_daddr <= up_es_saddr;
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up_hindex <= up_es_hmin;
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up_vindex <= up_es_vmin;
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end else if (up_fsm == ES_FSM_UPDATE) begin
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up_ut <= ~up_ut | up_ch_lpm_dfe_n;
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up_daddr <= up_daddr + 3'd4;
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if (up_heos_s == 1'b1) begin
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up_hindex <= up_es_hmin;
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end else if (up_ut == 1'b1) begin
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up_hindex <= up_hindex + up_es_hstep;
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end
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if (up_heos_s == 1'b1) begin
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up_vindex <= up_vindex + up_es_vstep;
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end
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end
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end
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end
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// read-modify-write
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_hdata <= 'd0;
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up_vdata <= 'd0;
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up_cdata <= 'd0;
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up_sdata <= 'd0;
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up_edata <= 'd0;
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end else begin
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if ((up_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_ready == 1'b1)) begin
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up_hdata <= up_es_rdata;
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end
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if ((up_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_ready == 1'b1)) begin
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up_vdata <= up_es_rdata;
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end
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if ((up_fsm == ES_FSM_CTRL_RRDY) && (up_es_ready == 1'b1)) begin
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up_cdata <= up_es_rdata;
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end
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if ((up_fsm == ES_FSM_SCNT_RRDY) && (up_es_ready == 1'b1)) begin
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up_sdata <= up_es_rdata;
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end
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if ((up_fsm == ES_FSM_ECNT_RRDY) && (up_es_ready == 1'b1)) begin
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up_edata <= up_es_rdata;
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end
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end
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end
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// request, start and ack
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assign up_start_s = up_es_req & ~up_req_d;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_req_d <= 1'b0;
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up_ack <= 1'b0;
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end else begin
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up_req_d <= up_es_req;
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if (up_fsm == ES_FSM_UPDATE) begin
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up_ack <= up_eos_s | ~up_es_req;
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end else begin
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up_ack <= 1'b0;
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end
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end
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end
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// es-fsm
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_fsm <= ES_FSM_IDLE;
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end else begin
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case (up_fsm)
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ES_FSM_IDLE: begin
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if (up_start_s == 1'b1) begin
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up_fsm <= ES_FSM_HOFFSET_READ;
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end else begin
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up_fsm <= ES_FSM_IDLE;
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end
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end
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ES_FSM_HOFFSET_READ: begin
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up_fsm <= ES_FSM_HOFFSET_RRDY;
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end
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ES_FSM_HOFFSET_RRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_HOFFSET_WRITE;
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end else begin
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up_fsm <= ES_FSM_HOFFSET_RRDY;
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end
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end
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ES_FSM_HOFFSET_WRITE: begin
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up_fsm <= ES_FSM_HOFFSET_WRDY;
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end
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ES_FSM_HOFFSET_WRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_VOFFSET_READ;
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end else begin
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up_fsm <= ES_FSM_HOFFSET_WRDY;
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end
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end
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ES_FSM_VOFFSET_READ: begin
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up_fsm <= ES_FSM_VOFFSET_RRDY;
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end
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ES_FSM_VOFFSET_RRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_VOFFSET_WRITE;
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end else begin
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up_fsm <= ES_FSM_VOFFSET_RRDY;
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end
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end
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ES_FSM_VOFFSET_WRITE: begin
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up_fsm <= ES_FSM_VOFFSET_WRDY;
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end
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ES_FSM_VOFFSET_WRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_CTRL_READ;
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end else begin
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up_fsm <= ES_FSM_VOFFSET_WRDY;
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end
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end
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ES_FSM_CTRL_READ: begin
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up_fsm <= ES_FSM_CTRL_RRDY;
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end
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ES_FSM_CTRL_RRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_START_WRITE;
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end else begin
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up_fsm <= ES_FSM_CTRL_RRDY;
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end
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end
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ES_FSM_START_WRITE: begin
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up_fsm <= ES_FSM_START_WRDY;
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end
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ES_FSM_START_WRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_STATUS_READ;
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end else begin
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up_fsm <= ES_FSM_START_WRDY;
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end
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end
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ES_FSM_STATUS_READ: begin
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up_fsm <= ES_FSM_STATUS_RRDY;
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end
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ES_FSM_STATUS_RRDY: begin
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if (up_es_ready == 1'b0) begin
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up_fsm <= ES_FSM_STATUS_RRDY;
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end else if (up_es_rdata[3:0] == 4'b0101) begin
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up_fsm <= ES_FSM_STOP_WRITE;
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end else begin
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up_fsm <= ES_FSM_STATUS_READ;
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end
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end
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ES_FSM_STOP_WRITE: begin
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up_fsm <= ES_FSM_STOP_WRDY;
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end
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ES_FSM_STOP_WRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_SCNT_READ;
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end else begin
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up_fsm <= ES_FSM_STOP_WRDY;
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end
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end
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ES_FSM_SCNT_READ: begin
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up_fsm <= ES_FSM_SCNT_RRDY;
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end
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ES_FSM_SCNT_RRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_ECNT_READ;
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end else begin
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up_fsm <= ES_FSM_SCNT_RRDY;
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end
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end
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ES_FSM_ECNT_READ: begin
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up_fsm <= ES_FSM_ECNT_RRDY;
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end
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ES_FSM_ECNT_RRDY: begin
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if (up_es_ready == 1'b1) begin
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up_fsm <= ES_FSM_AXI_WRITE;
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end else begin
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up_fsm <= ES_FSM_ECNT_RRDY;
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end
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end
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ES_FSM_AXI_WRITE: begin
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up_fsm <= ES_FSM_AXI_READY;
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end
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ES_FSM_AXI_READY: begin
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if (up_axi_bvalid == 1'b1) begin
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up_fsm <= ES_FSM_UPDATE;
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end else begin
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up_fsm <= ES_FSM_AXI_READY;
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end
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end
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ES_FSM_UPDATE: begin
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if ((up_eos_s == 1'b1) || (up_es_req == 1'b0)) begin
|
|
up_fsm <= ES_FSM_IDLE;
|
|
end else if (up_ut == 1'b1) begin
|
|
up_fsm <= ES_FSM_HOFFSET_READ;
|
|
end else begin
|
|
up_fsm <= ES_FSM_VOFFSET_READ;
|
|
end
|
|
end
|
|
default: begin
|
|
up_fsm <= ES_FSM_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// channel access
|
|
|
|
always @(negedge up_rstn or posedge up_clk) begin
|
|
if (up_rstn == 1'b0) begin
|
|
up_enb <= 'd0;
|
|
up_addr <= 'd0;
|
|
up_wr <= 'd0;
|
|
up_data <= 'd0;
|
|
end else begin
|
|
case (up_fsm)
|
|
ES_FSM_HOFFSET_READ: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_HOFFSET_ADDR;
|
|
up_wr <= 1'b0;
|
|
up_data <= 16'h0000;
|
|
end
|
|
ES_FSM_HOFFSET_WRITE: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_HOFFSET_ADDR;
|
|
up_wr <= 1'b1;
|
|
if (GTH_OR_GTX_N == 1) begin
|
|
up_data <= {up_hindex, up_hdata[3:0]};
|
|
end else begin
|
|
up_data <= {up_hdata[15:12], up_hindex};
|
|
end
|
|
end
|
|
ES_FSM_VOFFSET_READ: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_VOFFSET_ADDR;
|
|
up_wr <= 1'b0;
|
|
up_data <= 16'h0000;
|
|
end
|
|
ES_FSM_VOFFSET_WRITE: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_VOFFSET_ADDR;
|
|
up_wr <= 1'b1;
|
|
if (GTH_OR_GTX_N == 1) begin
|
|
up_data <= {up_vdata[15:11], up_vindex_s[7], up_ut_s, up_vindex_s[6:0], up_es_vrange};
|
|
end else begin
|
|
up_data <= {up_es_pscale, up_vdata[10:9], up_ut_s, up_vindex_s};
|
|
end
|
|
end
|
|
ES_FSM_CTRL_READ: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_CTRL_ADDR;
|
|
up_wr <= 1'b0;
|
|
up_data <= 16'h0000;
|
|
end
|
|
ES_FSM_START_WRITE: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_CTRL_ADDR;
|
|
up_wr <= 1'b1;
|
|
if (GTH_OR_GTX_N == 1) begin
|
|
up_data <= {6'd1, 2'b11, up_cdata[7:5], up_es_pscale};
|
|
end else begin
|
|
up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd1};
|
|
end
|
|
end
|
|
ES_FSM_STATUS_READ: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_STATUS_ADDR;
|
|
up_wr <= 1'b0;
|
|
up_data <= 16'h0000;
|
|
end
|
|
ES_FSM_STOP_WRITE: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_CTRL_ADDR;
|
|
up_wr <= 1'b1;
|
|
if (GTH_OR_GTX_N == 1) begin
|
|
up_data <= {6'd0, 2'b11, up_cdata[7:5], up_es_pscale};
|
|
end else begin
|
|
up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd0};
|
|
end
|
|
end
|
|
ES_FSM_SCNT_READ: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_SCNT_ADDR;
|
|
up_wr <= 1'b0;
|
|
up_data <= 16'h0000;
|
|
end
|
|
ES_FSM_ECNT_READ: begin
|
|
up_enb <= 1'b1;
|
|
up_addr <= ES_DRP_ECNT_ADDR;
|
|
up_wr <= 1'b0;
|
|
up_data <= 16'h0000;
|
|
end
|
|
default: begin
|
|
up_enb <= 1'b0;
|
|
up_addr <= 9'h000;
|
|
up_wr <= 1'b0;
|
|
up_data <= 16'h0000;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|