148 lines
4.0 KiB
Verilog
148 lines
4.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module axi_adxcvr_mdrp (
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input up_rstn,
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input up_clk,
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input [ 7:0] up_sel,
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input up_enb,
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input [15:0] up_rdata_in,
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input up_ready_in,
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input [15:0] up_rdata,
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input up_ready,
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output [15:0] up_rdata_out,
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output up_ready_out);
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// parameters
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parameter integer XCVR_ID = 0;
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parameter integer NUM_OF_LANES = 8;
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// internal registers
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reg [15:0] up_rdata_int = 'd0;
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reg up_ready_int = 'd0;
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reg up_ready_mi = 'd0;
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reg [15:0] up_rdata_i = 'd0;
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reg up_ready_i = 'd0;
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reg [15:0] up_rdata_m = 'd0;
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reg up_ready_m = 'd0;
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// internal signals
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wire up_ready_s;
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wire [15:0] up_rdata_mi_s;
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wire up_ready_mi_s;
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// disable if not selected
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assign up_rdata_out = up_rdata_int;
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assign up_ready_out = up_ready_int;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rdata_int <= 16'd0;
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up_ready_int <= 1'b0;
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end else begin
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case (up_sel)
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8'hff: begin
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up_rdata_int <= up_rdata_mi_s;
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up_ready_int <= up_ready_mi_s & ~up_ready_mi;
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end
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XCVR_ID: begin
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up_rdata_int <= up_rdata;
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up_ready_int <= up_ready;
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end
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default: begin
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up_rdata_int <= up_rdata_in;
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up_ready_int <= up_ready_in;
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end
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endcase
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_ready_mi <= 1'b0;
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end else begin
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up_ready_mi <= up_ready_mi_s;
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end
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end
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assign up_rdata_mi_s = up_rdata_m | up_rdata_i;
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assign up_ready_mi_s = up_ready_m & up_ready_i;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rdata_i <= 16'd0;
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up_ready_i <= 1'b0;
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end else begin
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if (up_ready_in == 1'b1) begin
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up_rdata_i <= up_rdata_in;
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up_ready_i <= 1'b1;
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end else if (up_enb == 1'b1) begin
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up_rdata_i <= 16'd0;
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up_ready_i <= 1'b0;
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end
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end
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end
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generate
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if (XCVR_ID < NUM_OF_LANES) begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rdata_m <= 16'd0;
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up_ready_m <= 1'b0;
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end else begin
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if (up_ready == 1'b1) begin
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up_rdata_m <= up_rdata;
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up_ready_m <= 1'b1;
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end else if (up_enb == 1'b1) begin
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up_rdata_m <= 16'd0;
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up_ready_m <= 1'b0;
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end
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end
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end
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end else begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rdata_m <= 16'd0;
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up_ready_m <= 1'b0;
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end else begin
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up_rdata_m <= 16'd0;
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up_ready_m <= 1'b1;
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end
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end
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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