389 lines
13 KiB
Verilog
389 lines
13 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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output spi_do,
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input spi_di,
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output spi_clk,
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output spi_enb,
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output usb_pd_reset,
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output usb_flash_prog_en,
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output fan_en,
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output fan_ctl,
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output adrv9002_mcssrc,
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inout [15:0] ext_gpio,
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inout [14:0] add_on_gpio,
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output add_on_power,
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inout [11:0] dgpio,
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input gp_int,
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output mode,
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output resetb,
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output clksrc,
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input vin_poe_valid_n,
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input vin_usb2_valid_n,
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input vin_usb1_valid_n,
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input fpga_ref_clk_n,
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input fpga_ref_clk_p,
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input fpga_mcs_in_n,
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input fpga_mcs_in_p,
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output dev_mcs_fpga_out_n,
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output dev_mcs_fpga_out_p,
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input rx1_dclk_in_n,
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input rx1_dclk_in_p,
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output rx1_enable,
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input rx1_idata_in_n,
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input rx1_idata_in_p,
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input rx1_qdata_in_n,
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input rx1_qdata_in_p,
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input rx1_strobe_in_n,
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input rx1_strobe_in_p,
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input rx2_dclk_in_n,
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input rx2_dclk_in_p,
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output rx2_enable,
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input rx2_idata_in_n,
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input rx2_idata_in_p,
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input rx2_qdata_in_n,
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input rx2_qdata_in_p,
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input rx2_strobe_in_n,
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input rx2_strobe_in_p,
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output tx1_dclk_out_n,
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output tx1_dclk_out_p,
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input tx1_dclk_in_n,
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input tx1_dclk_in_p,
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output tx1_enable,
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output tx1_idata_out_n,
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output tx1_idata_out_p,
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output tx1_qdata_out_n,
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output tx1_qdata_out_p,
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output tx1_strobe_out_n,
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output tx1_strobe_out_p,
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output tx2_dclk_out_n,
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output tx2_dclk_out_p,
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input tx2_dclk_in_n,
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input tx2_dclk_in_p,
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output tx2_enable,
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output tx2_idata_out_n,
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output tx2_idata_out_p,
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output tx2_qdata_out_n,
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output tx2_qdata_out_p,
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output tx2_strobe_out_n,
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output tx2_strobe_out_p,
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output rf_rx1a_mux_ctl,
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output rf_rx1b_mux_ctl,
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output rf_rx2a_mux_ctl,
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output rf_rx2b_mux_ctl,
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output rf_tx1_mux_ctl1,
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output rf_tx1_mux_ctl2,
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output rf_tx2_mux_ctl1,
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output rf_tx2_mux_ctl2,
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input s_1p0_rf_sns_p,
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input s_1p0_rf_sns_n,
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input s_1p8_rf_sns_p,
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input s_1p8_rf_sns_n,
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input s_1p3_rf_sns_p,
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input s_1p3_rf_sns_n,
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input s_5v0_rf_sns_p,
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input s_5v0_rf_sns_n,
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input s_2v5_sns_p,
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input s_2v5_sns_n,
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input s_vtt_ps_ddr4_sns_p,
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input s_vtt_ps_ddr4_sns_n,
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input s_1v2_ps_ddr4_sns_p,
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input s_1v2_ps_ddr4_sns_n,
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input s_0v85_mgtravcc_sns_p,
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input s_0v85_mgtravcc_sns_n,
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input s_5v0_sns_p,
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input s_5v0_sns_n,
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input s_1v2_sns_p,
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input s_1v2_sns_n,
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input s_1v8_mgtravtt_sns_p,
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input s_1v8_mgtravtt_sns_n
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);
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// internal registers
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reg mcs_sync_m = 'd0;
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reg [31:0] mcs_sync_pulse_period = 32'd1000; // 26us (ref_clk = 38.4M clk)
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reg [31:0] mcs_sync_pulse_delay = 32'd4000; // 104.1us (ref_clk = 38.4M clk)
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reg [31:0] mcs_sync_pulse_period_cnt = 32'd0;
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reg [31:0] mcs_sync_pulse_delay_cnt = 32'd0;
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reg [ 2:0] mcs_sync_pulse_num = 3'd0;
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reg mcs_sync_busy = 1'b0;
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reg mcs_out = 1'b0;
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [94:0] gpio_t;
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wire spi0_csn;
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wire fpga_ref_clk;
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wire fpga_mcs_in;
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wire mssi_sync;
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wire mcs_start;
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wire system_sync;
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wire mcs_or_system_sync_n;
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wire gpio_rx1_enable_in;
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wire gpio_rx2_enable_in;
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wire gpio_tx1_enable_in;
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wire gpio_tx2_enable_in;
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// assignments
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assign gpio_i[94:68] = gpio_o[94:68];
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assign gpio_i[64] = gpio_o[64];
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assign gpio_i[15:7] = gpio_o[15:7];
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assign gpio_i[3:1] = gpio_o[3:1];
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assign gpio_i[0] = gp_int;
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assign clksrc = gpio_o[1];
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assign mode = gpio_o[2];
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assign resetb = gpio_o[3];
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assign gpio_i[4] = vin_poe_valid_n;
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assign gpio_i[5] = vin_usb2_valid_n;
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assign gpio_i[6] = vin_usb1_valid_n;
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assign mssi_sync = mcs_sync_busy | gpio_o[7];
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assign usb_pd_reset = 1'b0;
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assign adrv9002_mcssrc = gpio_o[65];
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assign usb_flash_prog_en = gpio_o[66];
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assign fan_en = 1'b1;
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assign fan_ctl = gpio_o[67];
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assign rf_rx1a_mux_ctl = gpio_o[ 8];
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assign rf_rx1b_mux_ctl = gpio_o[ 9];
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assign rf_rx2a_mux_ctl = gpio_o[10];
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assign rf_rx2b_mux_ctl = gpio_o[11];
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assign rf_tx1_mux_ctl1 = gpio_o[12];
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assign rf_tx1_mux_ctl2 = gpio_o[13];
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assign rf_tx2_mux_ctl1 = gpio_o[14];
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assign rf_tx2_mux_ctl2 = gpio_o[15];
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assign spi_enb = spi0_csn;
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// instantiations
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ad_iobuf #(
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.DATA_WIDTH(16)
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) i_ext_gpio_buf (
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.dio_t (gpio_t[31:16]),
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.dio_i (gpio_o[31:16]),
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.dio_o (gpio_i[31:16]),
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.dio_p (ext_gpio));
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ad_iobuf #(
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.DATA_WIDTH(16)
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) i_iobuf (
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.dio_t ({gpio_t[47:32]}),
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.dio_i ({gpio_o[47:32]}),
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.dio_o ({gpio_i[47:32]}),
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.dio_p ({gpio_rx1_enable_in, // 47
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gpio_rx2_enable_in, // 46
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gpio_tx1_enable_in, // 45
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gpio_tx2_enable_in, // 44
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dgpio[11:0]})); // 43:32
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ad_iobuf #(
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.DATA_WIDTH(15)
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) i_iobuf_addon (
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.dio_t ({gpio_t[62:48]}),
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.dio_i ({gpio_o[62:48]}),
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.dio_o ({gpio_i[62:48]}),
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.dio_p (add_on_gpio));
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assign add_on_power = gpio_o[63];
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IBUFDS i_ibufgs_fpga_ref_clk (
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.I (fpga_ref_clk_p),
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.IB (fpga_ref_clk_n),
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.O (fpga_ref_clk));
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IBUFDS i_ibufgs_fpga_mcs_in (
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.I (fpga_mcs_in_p),
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.IB (fpga_mcs_in_n),
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.O (fpga_mcs_in));
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OBUFDS i_obufds_dev_mcs_fpga_in (
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.I (mcs_out),
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.O (dev_mcs_fpga_out_p),
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.OB (dev_mcs_fpga_out_n));
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// multi-chip or system synchronization
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// consider fpga_ref_clk = 38.4M (26.042n)
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// the MCS sync requires 6 pulses of min 10us with a in between delay of min 100us
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always @(posedge fpga_ref_clk) begin
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mcs_sync_m <= fpga_mcs_in;
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if (mcs_start) begin
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mcs_sync_busy <= 1'b1;
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mcs_sync_pulse_period_cnt <= mcs_sync_pulse_period;
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mcs_sync_pulse_delay_cnt <= mcs_sync_pulse_delay;
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mcs_sync_pulse_num <= 3'd0;
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mcs_out <= 1'b0;
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end else if (mcs_sync_busy == 1'b1) begin
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if (mcs_sync_pulse_period_cnt != 32'd0) begin
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mcs_sync_pulse_period_cnt <= mcs_sync_pulse_period_cnt - 32'd1;
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mcs_out <= 1'b1;
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end else if (mcs_sync_pulse_delay_cnt != 32'd0) begin
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mcs_sync_pulse_delay_cnt <= mcs_sync_pulse_delay_cnt - 32'd1;
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mcs_out <= 1'b0;
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end else begin
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if (mcs_sync_pulse_num < 5) begin
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mcs_sync_pulse_num <= mcs_sync_pulse_num + 3'd1;
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mcs_sync_pulse_period_cnt <= mcs_sync_pulse_period;
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mcs_sync_pulse_delay_cnt <= mcs_sync_pulse_delay;
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end else begin
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mcs_sync_busy <= 1'b0;
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end
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mcs_out <= 1'b0;
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end
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end
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end
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assign mcs_start = !mcs_sync_m & fpga_mcs_in & !mcs_sync_busy & mcs_or_system_sync_n;
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assign system_sync = fpga_mcs_in & !mcs_or_system_sync_n;
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assign mcs_or_system_sync_n = gpio_o[64];
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.spi0_csn(spi0_csn),
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.spi0_miso(spi_di),
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.spi0_mosi(spi_do),
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.spi0_sclk(spi_clk),
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.ref_clk (fpga_ref_clk),
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.mssi_sync (mssi_sync),
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.system_sync (system_sync),
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.tx_output_enable (1'b1),
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.rx1_dclk_in_n (rx1_dclk_in_n),
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.rx1_dclk_in_p (rx1_dclk_in_p),
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.rx1_idata_in_n (rx1_idata_in_n),
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.rx1_idata_in_p (rx1_idata_in_p),
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.rx1_qdata_in_n (rx1_qdata_in_n),
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.rx1_qdata_in_p (rx1_qdata_in_p),
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.rx1_strobe_in_n (rx1_strobe_in_n),
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.rx1_strobe_in_p (rx1_strobe_in_p),
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.rx2_dclk_in_n (rx2_dclk_in_n),
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.rx2_dclk_in_p (rx2_dclk_in_p),
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.rx2_idata_in_n (rx2_idata_in_n),
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.rx2_idata_in_p (rx2_idata_in_p),
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.rx2_qdata_in_n (rx2_qdata_in_n),
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.rx2_qdata_in_p (rx2_qdata_in_p),
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.rx2_strobe_in_n (rx2_strobe_in_n),
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.rx2_strobe_in_p (rx2_strobe_in_p),
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.tx1_dclk_out_n (tx1_dclk_out_n),
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.tx1_dclk_out_p (tx1_dclk_out_p),
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.tx1_dclk_in_n (tx1_dclk_in_n),
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.tx1_dclk_in_p (tx1_dclk_in_p),
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.tx1_idata_out_n (tx1_idata_out_n),
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.tx1_idata_out_p (tx1_idata_out_p),
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.tx1_qdata_out_n (tx1_qdata_out_n),
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.tx1_qdata_out_p (tx1_qdata_out_p),
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.tx1_strobe_out_n (tx1_strobe_out_n),
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.tx1_strobe_out_p (tx1_strobe_out_p),
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.tx2_dclk_out_n (tx2_dclk_out_n),
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.tx2_dclk_out_p (tx2_dclk_out_p),
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.tx2_dclk_in_n (tx2_dclk_in_n),
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.tx2_dclk_in_p (tx2_dclk_in_p),
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.tx2_idata_out_n (tx2_idata_out_n),
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.tx2_idata_out_p (tx2_idata_out_p),
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.tx2_qdata_out_n (tx2_qdata_out_n),
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.tx2_qdata_out_p (tx2_qdata_out_p),
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.tx2_strobe_out_n (tx2_strobe_out_n),
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.tx2_strobe_out_p (tx2_strobe_out_p),
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.rx1_enable (rx1_enable),
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.rx2_enable (rx2_enable),
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.tx1_enable (tx1_enable),
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.tx2_enable (tx2_enable),
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.gpio_rx1_enable_in (gpio_rx1_enable_in),
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.gpio_rx2_enable_in (gpio_rx2_enable_in),
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.gpio_tx1_enable_in (gpio_tx1_enable_in),
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.gpio_tx2_enable_in (gpio_tx2_enable_in),
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.s_1p0_rf_sns_p (s_1p0_rf_sns_p),
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.s_1p0_rf_sns_n (s_1p0_rf_sns_n),
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.s_1p8_rf_sns_p (s_1p8_rf_sns_p),
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.s_1p8_rf_sns_n (s_1p8_rf_sns_n),
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.s_1p3_rf_sns_p (s_1p3_rf_sns_p),
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.s_1p3_rf_sns_n (s_1p3_rf_sns_n),
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.s_5v0_rf_sns_p (s_5v0_rf_sns_p),
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.s_5v0_rf_sns_n (s_5v0_rf_sns_n),
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.s_2v5_sns_p (s_2v5_sns_p),
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.s_2v5_sns_n (s_2v5_sns_n),
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.s_vtt_ps_ddr4_sns_p (s_vtt_ps_ddr4_sns_p),
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.s_vtt_ps_ddr4_sns_n (s_vtt_ps_ddr4_sns_n),
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.s_1v2_ps_ddr4_sns_p (s_1v2_ps_ddr4_sns_p),
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.s_1v2_ps_ddr4_sns_n (s_1v2_ps_ddr4_sns_n),
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.s_0v85_mgtravcc_sns_p (s_0v85_mgtravcc_sns_p),
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.s_0v85_mgtravcc_sns_n (s_0v85_mgtravcc_sns_n),
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.s_5v0_sns_p (s_5v0_sns_p),
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.s_5v0_sns_n (s_5v0_sns_n),
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.s_1v2_sns_p (s_1v2_sns_p),
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.s_1v2_sns_n (s_1v2_sns_n),
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.s_1v8_mgtravtt_sns_p (s_1v8_mgtravtt_sns_p),
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.s_1v8_mgtravtt_sns_n (s_1v8_mgtravtt_sns_n));
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endmodule
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