Istvan Csomortani bb185296d7 fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. ... The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells. This is a the maximum BRAM FIFO depth in case of the VC707.		2015-04-23 18:00:00 +03:00
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common	fmcadc2: Connect the second CS line for the external SPI interface	2015-04-15 19:08:17 +03:00
vc707	fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples.	2015-04-23 18:00:00 +03:00
zc706	Makefile: Added top level Makefile. Modified behavior of clean and clean-all	2015-04-17 17:22:38 +03:00
Makefile	Makefile: Added top level Makefile. Modified behavior of clean and clean-all	2015-04-17 17:22:38 +03:00