110 lines
3.3 KiB
VHDL
110 lines
3.3 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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--
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-- In this HDL repository, there are many different and unique modules, consisting
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-- of various HDL (Verilog or VHDL) components. The individual modules are
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-- developed independently, and may be accompanied by separate and unique license
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-- terms.
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--
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-- The user should read each of these license terms, and understand the
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-- freedoms and responsabilities that he or she has by using this source/core.
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--
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-- This core is distributed in the hope that it will be useful, but WITHOUT ANY
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-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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-- A PARTICULAR PURPOSE.
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--
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-- Redistribution and use of source or resulting binaries, with or without modification
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-- of this file, are permitted under one of the following two license terms:
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--
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-- 1. The GNU General Public License version 2 as published by the
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-- Free Software Foundation, which can be found in the top level directory
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-- of this repository (LICENSE_GPL2), and also online at:
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-- <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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--
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-- OR
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--
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-- 2. An ADI specific BSD license, which can be found in the top level directory
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-- of this repository (LICENSE_ADIBSD), and also on-line at:
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-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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-- This will allow to generate bit files and not release the source code,
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-- as long as it attaches to an ADI device.
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--
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.dma_fifo;
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entity axi_streaming_dma_tx_fifo is
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generic (
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RAM_ADDR_WIDTH : integer := 3;
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FIFO_DWIDTH : integer := 32
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);
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port (
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clk : in std_logic;
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resetn : in std_logic;
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fifo_reset : in std_logic;
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-- Enable DMA interface
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enable : in Boolean;
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-- Write port
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s_axis_aclk : in std_logic;
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s_axis_tready : out std_logic;
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s_axis_tdata : in std_logic_vector(FIFO_DWIDTH-1 downto 0);
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s_axis_tlast : in std_logic;
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s_axis_tvalid : in std_logic;
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-- Read port
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out_stb : out std_logic;
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out_ack : in std_logic;
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out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0)
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);
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end;
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architecture imp of axi_streaming_dma_tx_fifo is
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signal in_ack : std_logic;
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signal drain_dma : Boolean;
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begin
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fifo: entity dma_fifo
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generic map (
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RAM_ADDR_WIDTH => RAM_ADDR_WIDTH,
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FIFO_DWIDTH => FIFO_DWIDTH
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)
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port map (
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clk => clk,
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resetn => resetn,
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fifo_reset => fifo_reset,
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in_stb => s_axis_tvalid,
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in_ack => in_ack,
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in_data => s_axis_tdata,
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out_stb => out_stb,
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out_ack => out_ack,
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out_data => out_data
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);
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drain_process: process (s_axis_aclk) is
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variable enable_d1 : Boolean;
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begin
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if rising_edge(s_axis_aclk) then
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if resetn = '0' then
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drain_dma <= False;
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else
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if s_axis_tlast = '1' then
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drain_dma <= False;
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elsif enable_d1 and enable then
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drain_dma <= True;
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end if;
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enable_d1 := enable;
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end if;
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end if;
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end process;
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s_axis_tready <= '1' when in_ack = '1' or drain_dma else '0';
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end;
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