pluto_hdl_adi/library/xilinx
Lars-Peter Clausen de4fe30238 library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size
The external s_axi_{awaddr,araddr} signals that are connect to the core
have their width set according to the specified size of the register map.

If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently
is for many cores) the MSBs of those signals are left unconnected, which
generates a warning.

To avoid this make sure that the signal width matches the declared register
map size.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-01 15:21:25 +02:00
..
axi_adcfifo license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
axi_adxcvr library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size 2017-08-01 15:21:25 +02:00
axi_dacfifo hdlmake.pl - updates 2017-07-20 15:11:21 -04:00
axi_xcvrlb library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size 2017-08-01 15:21:25 +02:00
common hdlmake.pl- remove ad_lvds 2017-07-26 10:32:44 -04:00
util_adxcvr util_adxcvr: Bring back channel 8 2017-06-29 13:16:48 +02:00