pluto_hdl_adi/projects/ad9739a_fmc/zc706/system_top.v

198 lines
6.3 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [14:0] gpio_bd,
output hdmi_out_clk,
output hdmi_vsync,
output hdmi_hsync,
output hdmi_data_e,
output [23:0] hdmi_data,
output spdif,
inout iic_scl,
inout iic_sda,
input dac_clk_in_p,
input dac_clk_in_n,
output dac_clk_out_p,
output dac_clk_out_n,
output [13:0] dac_data_out_a_p,
output [13:0] dac_data_out_a_n,
output [13:0] dac_data_out_b_p,
output [13:0] dac_data_out_b_n,
output spi_csn_clk,
output spi_csn_dac,
output spi_clk,
output spi_mosi,
input spi_miso);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
// assignments
assign spi_csn_clk = spi0_csn[0];
assign spi_csn_dac = spi0_csn[1];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_data_out_a_n (dac_data_out_a_n),
.dac_data_out_a_p (dac_data_out_a_p),
.dac_data_out_b_n (dac_data_out_b_n),
.dac_data_out_b_p (dac_data_out_b_p),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_13 (1'b0),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************