171 lines
5.7 KiB
Verilog
171 lines
5.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_gt #(
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parameter integer GTH_OR_GTX_N = 0) (
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// drp interface
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output reg up_drp_qpll0_sel,
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output reg up_drp_qpll0_wr,
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output reg [11:0] up_drp_qpll0_addr,
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output reg [15:0] up_drp_qpll0_wdata,
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input [15:0] up_drp_qpll0_rdata,
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input up_drp_qpll0_ready,
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output reg up_drp_qpll1_sel,
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output reg up_drp_qpll1_wr,
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output reg [11:0] up_drp_qpll1_addr,
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output reg [15:0] up_drp_qpll1_wdata,
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input [15:0] up_drp_qpll1_rdata,
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input up_drp_qpll1_ready,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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// internal registers
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reg up_drp_qpll0_status = 'd0;
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reg up_drp_qpll0_rwn = 'd0;
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reg [15:0] up_drp_qpll0_rdata_hold = 'd0;
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reg up_drp_qpll1_status = 'd0;
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reg up_drp_qpll1_rwn = 'd0;
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reg [15:0] up_drp_qpll1_rdata_hold = 'd0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h10) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h10) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_drp_qpll0_sel <= 'd0;
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up_drp_qpll0_wr <= 'd0;
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up_drp_qpll0_status <= 'd0;
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up_drp_qpll0_rwn <= 'd0;
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up_drp_qpll0_addr <= 'd0;
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up_drp_qpll0_wdata <= 'd0;
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up_drp_qpll0_rdata_hold <= 'd0;
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up_drp_qpll1_sel <= 'd0;
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up_drp_qpll1_wr <= 'd0;
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up_drp_qpll1_status <= 'd0;
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up_drp_qpll1_rwn <= 'd0;
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up_drp_qpll1_addr <= 'd0;
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up_drp_qpll1_wdata <= 'd0;
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up_drp_qpll1_rdata_hold <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_drp_qpll0_sel <= 1'b1;
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up_drp_qpll0_wr <= ~up_wdata[28];
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end else begin
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up_drp_qpll0_sel <= 1'b0;
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up_drp_qpll0_wr <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_drp_qpll0_status <= 1'b1;
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end else if (up_drp_qpll0_ready == 1'b1) begin
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up_drp_qpll0_status <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_drp_qpll0_rwn <= up_wdata[28];
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up_drp_qpll0_addr <= up_wdata[27:16];
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up_drp_qpll0_wdata <= up_wdata[15:0];
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end
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if (up_drp_qpll0_ready == 1'b1) begin
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up_drp_qpll0_rdata_hold <= up_drp_qpll0_rdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
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up_drp_qpll1_sel <= 1'b1;
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up_drp_qpll1_wr <= ~up_wdata[28];
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end else begin
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up_drp_qpll1_sel <= 1'b0;
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up_drp_qpll1_wr <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
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up_drp_qpll1_status <= 1'b1;
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end else if (up_drp_qpll1_ready == 1'b1) begin
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up_drp_qpll1_status <= 1'b0;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
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up_drp_qpll1_rwn <= up_wdata[28];
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up_drp_qpll1_addr <= up_wdata[27:16];
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up_drp_qpll1_wdata <= up_wdata[15:0];
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end
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if (up_drp_qpll1_ready == 1'b1) begin
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up_drp_qpll1_rdata_hold <= up_drp_qpll1_rdata;
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h14: up_rdata <= {3'd0, up_drp_qpll0_rwn,
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up_drp_qpll0_addr, up_drp_qpll0_wdata};
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8'h15: up_rdata <= {15'd0, up_drp_qpll0_status, up_drp_qpll0_rdata};
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8'h24: up_rdata <= {3'd0, up_drp_qpll1_rwn,
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up_drp_qpll1_addr, up_drp_qpll1_wdata};
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8'h25: up_rdata <= {15'd0, up_drp_qpll1_status, up_drp_qpll1_rdata};
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8'h3a: up_rdata <= GTH_OR_GTX_N;
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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