125 lines
3.6 KiB
Verilog
125 lines
3.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_pmod #(
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parameter ID = 0) (
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input pmod_clk,
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output pmod_rst,
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input [31:0] pmod_signal_freq,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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localparam PCORE_VERSION = 32'h00010001;
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// internal registers
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reg [31:0] up_scratch = 'd0;
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reg up_resetn = 'd0;
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// internal signals
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wire [31:0] up_pmod_signal_freq_s;
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wire up_wreq_s;
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wire up_rreq_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0;
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assign up_preset_s = ~up_resetn;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_resetn <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_resetn <= up_wdata[0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00: up_rdata <= PCORE_VERSION;
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8'h01: up_rdata <= ID;
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8'h02: up_rdata <= up_scratch;
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8'h03: up_rdata <= up_pmod_signal_freq_s;
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8'h10: up_rdata <= up_resetn;
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// resets
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ad_rst i_adc_rst_reg (.preset(up_preset_s), .clk(pmod_clk), .rst(pmod_rst));
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// adc control & status
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up_xfer_status #(.DATA_WIDTH(32)) i_pmod_xfer_status (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_status (up_pmod_signal_freq_s),
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.d_rst (pmod_rst),
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.d_clk (pmod_clk),
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.d_data_status (pmod_signal_freq));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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