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Adrian Costina 698e9f4757 Added phys_opt_design step for fixing timing 
The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
 		2014-03-19 16:42:44 +02:00
library axi_dmac: Fix Vivado warnings 2014-03-18 20:59:13 +01:00
projects Added phys_opt_design step for fixing timing 2014-03-19 16:42:44 +02:00
.gitignore added gitignore 2014-03-05 10:47:16 -05:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Update README.md 2014-03-13 14:03:15 -04:00

README.md

hdl

Analog Devices HDL libraries and projects

http://wiki.analog.com/resources/fpga/docs/hdl/github

http://wiki.analog.com/resources/fpga/docs/hdl/regmap