Lars-Peter Clausen de4fe30238 library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size ... The external s_axi_{awaddr,araddr} signals that are connect to the core have their width set according to the specified size of the register map. If the s_axi_{awaddr,araddr} signal of the core is wider (as it currently is for many cores) the MSBs of those signals are left unconnected, which generates a warning. To avoid this make sure that the signal width matches the declared register map size. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-08-01 15:21:25 +02:00
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bd	axi_clkgen: Propagate clock settings to output pins	2017-04-20 20:36:33 +02:00
Makefile	updated makefiles	2016-12-09 23:06:41 +02:00
axi_clkgen.v	library: Match s_axi_{awaddr,araddr} signal width to peripheral memory map size	2017-08-01 15:21:25 +02:00
axi_clkgen_constr.xdc	library- drp moved to up clock	2015-06-01 13:39:26 -04:00
axi_clkgen_ip.tcl	axi_clkgen: Infer CLKIN period	2017-04-20 20:36:15 +02:00