102 lines
2.6 KiB
Makefile
102 lines
2.6 KiB
Makefile
####################################################################################
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## Copyright (c) 2018 - 2021 Analog Devices, Inc.
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## SPDX short identifier: BSD-1-Clause
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####################################################################################
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# Assumes this file is in library/scripts/library.mk
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HDL_LIBRARY_PATH := $(subst scripts/library.mk,,$(lastword $(MAKEFILE_LIST)))
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include $(HDL_LIBRARY_PATH)../quiet.mk
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CASE_INCLUDE := $(wildcard temporary_case_dependencies.mk)
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ifneq ($(CASE_INCLUDE),)
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include temporary_case_dependencies.mk
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endif
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VIVADO := vivado -mode batch -source
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CLEAN_TARGET += *.cache
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CLEAN_TARGET += *.data
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CLEAN_TARGET += *.xpr
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CLEAN_TARGET += *.log
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CLEAN_TARGET += component.xml
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CLEAN_TARGET += *.jou
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CLEAN_TARGET += xgui
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CLEAN_TARGET += *.ip_user_files
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CLEAN_TARGET += *.srcs
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CLEAN_TARGET += *.hw
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CLEAN_TARGET += *.sim
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CLEAN_TARGET += .Xil
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CLEAN_TARGET += .timestamp_intel
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CLEAN_TARGET += *.hbs
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CLEAN_TARGET += tb/*.log
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CLEAN_TARGET += tb/*.xml
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CLEAN_TARGET += tb/*.jou
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CLEAN_TARGET += tb/*.dir
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CLEAN_TARGET += tb/*.pb
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CLEAN_TARGET += tb/*.vcd
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CLEAN_TARGET += tb/*.wdb
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CLEAN_TARGET += tb/dcv.
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CLEAN_TARGET += tb/vsim.wlf
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CLEAN_TARGET += tb/work
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CLEAN_TARGET += tb/vcd
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CLEAN_TARGET += tb/run
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CLEAN_TARGET += tb/libraries
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CLEAN_TARGET += tb/.Xil
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CLEAN_TARGET += tb/xsim_gui_cmd.tcl
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CLEAN_TARGET += tb/libraries
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GENERIC_DEPS += $(HDL_LIBRARY_PATH)../scripts/adi_env.tcl
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.PHONY: all intel intel_dep xilinx xilinx_dep clean clean-all
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all: intel xilinx
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clean: clean-all
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clean-all:
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$(call clean, \
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$(CLEAN_TARGET), \
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$(HL)$(LIBRARY_NAME)$(NC) library)
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ifneq ($(INTEL_DEPS),)
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INTEL_DEPS += $(GENERIC_DEPS)
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INTEL_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_intel.tcl
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INTEL_DEPS += $(foreach dep,$(INTEL_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/.timestamp_intel)
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intel: intel_dep .timestamp_intel
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.timestamp_intel: $(INTEL_DEPS)
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touch $@
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intel_dep:
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@for lib in $(INTEL_LIB_DEPS); do \
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$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} intel || exit $$?; \
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done
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endif
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ifneq ($(XILINX_DEPS),)
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XILINX_DEPS += $(GENERIC_DEPS)
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XILINX_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_xilinx.tcl
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XILINX_DEPS += $(foreach dep,$(XILINX_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/component.xml)
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xilinx: xilinx_dep component.xml
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component.xml: $(XILINX_DEPS)
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-rm -rf $(CLEAN_TARGET)
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$(call build, \
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$(VIVADO) $(LIBRARY_NAME)_ip.tcl, \
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$(LIBRARY_NAME)_ip.log, \
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$(HL)$(LIBRARY_NAME)$(NC) library)
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xilinx_dep:
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@for lib in $(XILINX_LIB_DEPS); do \
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$(MAKE) -C $(HDL_LIBRARY_PATH)$${lib} xilinx || exit $$?; \
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done
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@for intf in $(XILINX_INTERFACE_DEPS); do \
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$(MAKE) -C $(HDL_LIBRARY_PATH)$${intf} xilinx || exit $$?; \
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done
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endif
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