141 lines
4.8 KiB
Verilog
141 lines
4.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// Input must be RGB or CrYCb in that order, output is CrY/CbY
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module ad_ss_422to444 #(
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parameter CR_CB_N = 0,
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parameter DELAY_DATA_WIDTH = 16) (
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// 422 inputs
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input clk,
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input s422_de,
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input [DW:0] s422_sync,
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input [15:0] s422_data,
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// 444 outputs
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output reg [DW:0] s444_sync,
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output reg [23:0] s444_data);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// internal registers
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reg cr_cb_sel = 'd0;
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reg s422_de_d = 'd0;
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reg [DW:0] s422_sync_d = 'd0;
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reg s422_de_2d = 'd0;
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reg [7:0] s422_Y_d;
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reg [7:0] s422_CbCr_d;
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reg [7:0] s422_CbCr_2d;
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reg [ 8:0] s422_CbCr_avg;
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// internal wires
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wire [ 7:0] s422_Y;
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wire [ 7:0] s422_CbCr;
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// Input format is
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// [15:8] Cb/Cr
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// [ 7:0] Y
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//
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// Output format is
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// [23:15] Cr
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// [16: 8] Y
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// [ 7: 0] Cb
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assign s422_Y = s422_data[7:0];
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assign s422_CbCr = s422_data[15:8];
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// first data on de assertion is cb (0x0), then cr (0x1).
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// previous data is held when not current
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always @(posedge clk) begin
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if (s422_de_d == 1'b1) begin
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cr_cb_sel <= ~cr_cb_sel;
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end else begin
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cr_cb_sel <= CR_CB_N;
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end
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end
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// pipe line stages
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always @(posedge clk) begin
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s422_de_d <= s422_de;
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s422_sync_d <= s422_sync;
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s422_de_2d <= s422_de_d;
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s422_Y_d <= s422_Y;
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s422_CbCr_d <= s422_CbCr;
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s422_CbCr_2d <= s422_CbCr_d;
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end
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// If both the left and the right sample are valid do the average, otherwise
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// use the only valid.
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always @(s422_de_2d, s422_de, s422_CbCr, s422_CbCr_2d)
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begin
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if (s422_de == 1'b1 && s422_de_2d)
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s422_CbCr_avg <= s422_CbCr + s422_CbCr_2d;
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else if (s422_de == 1'b1)
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s422_CbCr_avg <= {s422_CbCr, 1'b0};
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else
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s422_CbCr_avg <= {s422_CbCr_2d, 1'b0};
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end
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// 444 outputs
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always @(posedge clk) begin
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s444_sync <= s422_sync_d;
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s444_data[15:8] <= s422_Y_d;
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if (cr_cb_sel) begin
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s444_data[23:16] <= s422_CbCr_d;
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s444_data[ 7: 0] <= s422_CbCr_avg[8:1];
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end else begin
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s444_data[23:16] <= s422_CbCr_avg[8:1];
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s444_data[ 7: 0] <= s422_CbCr_d;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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