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pluto_hdl_adi/library/jesd204/jesd204_rx
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Laszlo Nagy dd58759cd8 jesd204: Intel: NP12 support 
Dual clock mode is introduced in link layer to support different
datapath widths on the transport layer than on physical layer.

- Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b
- Device clock : Link clock * input data path width / output datapath width

Supports four clock configurations, single or dual clock mode with or
without external device clock.

The configuration interface reflects the dual clock domain.
 		2021-02-05 15:24:15 +02:00
..
bd jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
Makefile jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
align_mux.v jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
elastic_buffer.v jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
error_monitor.v jesd204_rx: 64b mode support for receive peripheral 2020-02-10 09:47:07 +02:00
jesd204_ilas_monitor.v jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
jesd204_lane_latency_monitor.v jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
jesd204_rx.v jesd204: Expose core synthesis parameters through registers 2021-02-05 15:24:15 +02:00
jesd204_rx_cgs.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
jesd204_rx_constr.sdc jesd204: Intel: NP12 support 2021-02-05 15:24:15 +02:00
jesd204_rx_constr.ttcl jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
jesd204_rx_ctrl.v jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement 2021-02-05 15:24:15 +02:00
jesd204_rx_ctrl_64b.v jesd204_rx: Interrupt for unexpected lane status error 2020-07-31 11:43:41 +03:00
jesd204_rx_frame_align.v jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
jesd204_rx_header.v jesd204_rx: 64b mode support for receive peripheral 2020-02-10 09:47:07 +02:00
jesd204_rx_hw.tcl jesd204: Intel: NP12 support 2021-02-05 15:24:15 +02:00
jesd204_rx_ip.tcl jesd204: Expose core synthesis parameters through registers 2021-02-05 15:24:15 +02:00
jesd204_rx_lane.v jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00
jesd204_rx_lane_64b.v jesd204: Xilinx: NP=12 support 2021-02-05 15:24:15 +02:00