6da9c65a08
Right now there is always a period of one clock cycle where we can not transfer any data when switching between two transfers. This patch modifies the data mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md |
README.md
hdl
HDL libraries and projects