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Istvan Csomortani 6dbbe2f1ca altera/ad_mem_asym: Fix grounded bus for marco instance 
The "'b0" constant will be translate as a 32 bit width vector by
ModelSim, and will throw a buswidth mismatch error. Tie the data_b
bus to zero, using its width parameter.
 		2017-05-25 15:12:09 +03:00
library altera/ad_mem_asym: Fix grounded bus for marco instance 2017-05-25 15:12:09 +03:00
projects m2k: Add scale correction option. Update parameters 2017-05-24 15:59:24 +03:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

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