205 lines
6.0 KiB
Verilog
205 lines
6.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_dec256sinc24b (
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input clk, /* used to clk filter */
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input reset, /* used to reset filter */
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input data_in, /* input data to be filtered */
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output reg [15:0] data_out, /* filtered output */
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output reg data_en,
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input [15:0] dec_rate);
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/* Data is read on positive clk edge */
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reg [36:0] data_int = 37'h0;
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reg [36:0] acc1 = 37'h0;
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reg [36:0] acc2 = 37'h0;
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reg [36:0] acc3 = 37'h0;
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reg [36:0] acc3_d = 37'h0;
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reg [36:0] diff1_d = 37'h0;
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reg [36:0] diff2_d = 37'h0;
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reg [15:0] word_count = 16'h0;
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reg word_en = 1'b0;
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reg enable = 1'b0;
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wire [36:0] acc1_s;
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wire [36:0] acc2_s;
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wire [36:0] acc3_s;
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wire [36:0] diff1_s;
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wire [36:0] diff2_s;
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wire [36:0] diff3_s;
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/* Perform the Sinc action */
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always @(data_in) begin
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if (data_in==0)
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data_int <= 37'd0;
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else /* change 0 to a -1 for twos complement */
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data_int <= 37'd1;
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end
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/* Accumulator (Integrator) Perform the accumulation (IIR) at the speed of
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* the modulator. Z = one sample delay MCLKOUT = modulators conversion
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* bit rate */
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always @(negedge clk) begin
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if (reset == 1'b1) begin
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/* initialize acc registers on reset */
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acc1 <= 37'd0;
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acc2 <= 37'd0;
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acc3 <= 37'd0;
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end else begin
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/* perform accumulation process */
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acc1 <= acc1_s;
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acc2 <= acc2_s;
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acc3 <= acc3_s;
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end
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end
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assign acc1_s = acc1 + data_int;
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assign acc2_s = acc2 + acc1;
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assign acc3_s = acc3 + acc2;
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/* decimation stage (MCLKOUT/WORD_CLK) */
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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word_count <= 16'd0;
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end else begin
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if (word_count == (dec_rate - 1))
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word_count <= 16'd0;
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else
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word_count <= word_count + 16'b1;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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word_en <= 1'b0;
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end else begin
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if (word_count == (dec_rate/2 - 1))
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word_en <= 1'b1;
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else
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word_en <= 1'b0;
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end
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end
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/* Differentiator (including decimation stage)
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* Perform the differentiation stage (FIR) at a lower speed.
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* Z = one sample delay WORD_EN = output word rate */
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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diff1_d <= 37'd0;
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diff2_d <= 37'd0;
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acc3_d <= 37'b0;
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end else if (word_en == 1'b1) begin
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acc3_d <= acc3;
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diff1_d <= diff1_s;
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diff2_d <= diff2_s;
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end
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end
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assign diff1_s = acc3_s - acc3;
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assign diff2_s = diff1_s - diff1_d;
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assign diff3_s = diff2_s - diff2_d;
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/* Clock the Sinc output into an output register
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* WORD_EN = output word rate */
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always @(posedge clk) begin
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if (word_en == 1'b1) begin
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case (dec_rate)
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16'd32: begin
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data_out <= (diff3_s[15:0] == 16'h8000) ? 16'hFFFF : {diff3_s[14:0], 1'b0};
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end
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16'd64: begin
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data_out <= (diff3_s[18:2] == 17'h10000) ? 16'hFFFF : diff3_s[17:2];
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end
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16'd128: begin
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data_out <= (diff3_s[21:5] == 17'h10000) ? 16'hFFFF : diff3_s[20:5];
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end
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16'd256: begin
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data_out <= (diff3_s[24:8] == 17'h10000) ? 16'hFFFF : diff3_s[23:8];
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end
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16'd512: begin
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data_out <= (diff3_s[27:11] == 17'h10000) ? 16'hFFFF : diff3_s[26:11];
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end
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16'd1024: begin
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data_out <= (diff3_s[30:14] == 17'h10000) ? 16'hFFFF : diff3_s[29:14];
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end
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16'd2048: begin
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data_out <= (diff3_s[33:17] == 17'h10000) ? 16'hFFFF : diff3_s[32:17];
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end
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16'd4096: begin
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data_out <= (diff3_s[36:20] == 17'h10000) ? 16'hFFFF : diff3_s[35:20];
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end
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default:begin
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data_out <= (diff3_s[24:8] == 17'h10000) ? 16'hFFFF : diff3_s[23:8];
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end
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endcase
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end
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end
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/* Synchronize Data Output */
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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data_en <= 1'b0;
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enable <= 1'b1;
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end else begin
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if ((word_count == (dec_rate/2 - 1)) && (enable == 1'b1)) begin
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data_en <= 1'b1;
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enable <= 1'b0;
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end else if ((word_count == (dec_rate - 1)) && (enable == 1'b0)) begin
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data_en <= 1'b0;
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enable <= 1'b1;
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end else
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data_en <= 1'b0;
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end
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end
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endmodule
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