157 lines
5.1 KiB
Verilog
157 lines
5.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// This is the LVDS/DDR interface, note that overrange is independent of data path,
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// software will not be able to relate overrange to a specific sample!
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`timescale 1ns/100ps
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module axi_ad9265_if #(
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parameter FPGA_TECHNOLOGY = 0,
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parameter IO_DELAY_GROUP = "adc_if_delay_group",
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parameter DELAY_REFCLK_FREQUENCY = 200) (
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// adc interface (clk, data, over-range)
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// nominal clock 125 MHz, up to 300 MHz
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input adc_clk_in_p,
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input adc_clk_in_n,
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input [ 7:0] adc_data_in_p,
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input [ 7:0] adc_data_in_n,
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input adc_or_in_p,
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input adc_or_in_n,
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// interface outputs
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output adc_clk,
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output reg [15:0] adc_data,
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output reg adc_or,
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output reg adc_status,
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// delay control signals
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input up_clk,
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input [ 8:0] up_dld,
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input [44:0] up_dwdata,
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output [44:0] up_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// internal registers
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reg [ 7:0] adc_data_p = 'd0;
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reg [ 7:0] adc_data_n = 'd0;
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reg adc_or_p = 'd0;
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reg adc_or_n = 'd0;
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// internal signals
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wire [ 7:0] adc_data_p_s;
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wire [ 7:0] adc_data_n_s;
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wire adc_or_p_s;
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wire adc_or_n_s;
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genvar l_inst;
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always @(posedge adc_clk)
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begin
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adc_status <= 1'b1;
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adc_or <= adc_or_p_s | adc_or_n_s;
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adc_data <= { adc_data_p_s[7], adc_data_n_s[7], adc_data_p_s[6], adc_data_n_s[6], adc_data_p_s[5], adc_data_n_s[5], adc_data_p_s[4], adc_data_n_s[4], adc_data_p_s[3], adc_data_n_s[3], adc_data_p_s[2], adc_data_n_s[2], adc_data_p_s[1], adc_data_n_s[1], adc_data_p_s[0], adc_data_n_s[0]};
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end
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// data interface
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generate
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for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
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ad_data_in #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP),
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.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
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i_adc_data (
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.rx_clk (adc_clk),
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.rx_data_in_p (adc_data_in_p[l_inst]),
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.rx_data_in_n (adc_data_in_n[l_inst]),
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.rx_data_p (adc_data_p_s[l_inst]),
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.rx_data_n (adc_data_n_s[l_inst]),
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.up_clk (up_clk),
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.up_dld (up_dld[l_inst]),
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.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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end
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endgenerate
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// over-range interface
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ad_data_in #(
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (IO_DELAY_GROUP),
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.REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY))
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i_adc_or (
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.rx_clk (adc_clk),
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.rx_data_in_p (adc_or_in_p),
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.rx_data_in_n (adc_or_in_n),
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.rx_data_p (adc_or_p_s),
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.rx_data_n (adc_or_n_s),
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.up_clk (up_clk),
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.up_dld (up_dld[8]),
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.up_dwdata (up_dwdata[44:40]),
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.up_drdata (up_drdata[44:40]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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// clock
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ad_data_clk
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i_adc_clk (
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.rst (1'b0),
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.locked (),
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.clk_in_p (adc_clk_in_p),
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.clk_in_n (adc_clk_in_n),
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.clk (adc_clk));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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