Laszlo Nagy 08b0d19731 axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks ... Depending on FPGA technology the physical layer uses different deserialization factors and corresponding clock division factors to divide the source synchronous interface clock. This must be exposed to software so it can act on it while setting the DDS rate. Xilinx CMOS clock ratio - 4 Xilinx LVDS clock ratio - 4 Intel CMOS clock ratio - 1		2021-05-26 15:44:45 +03:00
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adrv9001_rx.v	axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks	2021-05-26 15:44:45 +03:00
adrv9001_tx.v	axi_adrv9001: Populate correct ratio of the SSI interface and user interface clocks	2021-05-26 15:44:45 +03:00