154 lines
4.8 KiB
Verilog
154 lines
4.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module adrv9001_rx #(
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parameter CMOS_LVDS_N = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter NUM_LANES = 3,
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parameter DRP_WIDTH = 5,
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parameter IODELAY_CTRL = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group"
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) (
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// device interface
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input rx_dclk_in_n_NC,
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input rx_dclk_in_p_dclk_in,
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input rx_idata_in_n_idata0,
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input rx_idata_in_p_idata1,
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input rx_qdata_in_n_qdata2,
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input rx_qdata_in_p_qdata3,
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input rx_strobe_in_n_NC,
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input rx_strobe_in_p_strobe_in,
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// internal reset and clocks
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input adc_rst,
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output adc_clk,
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output adc_clk_div,
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output [7:0] adc_data_0,
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output [7:0] adc_data_1,
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output [7:0] adc_data_2,
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output [7:0] adc_data_3,
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output [7:0] adc_data_strobe,
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output adc_valid,
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output [31:0] adc_clk_ratio,
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// delay interface (for IDELAY macros)
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input up_clk,
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input [NUM_LANES-1:0] up_adc_dld,
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input [DRP_WIDTH*NUM_LANES-1:0] up_adc_dwdata,
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output [DRP_WIDTH*NUM_LANES-1:0] up_adc_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked,
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input mssi_sync,
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output ssi_sync_out,
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input ssi_sync_in,
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output ssi_rst
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);
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reg [3:0] valid_gen = 4'b0001;
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wire [4:0] gpio_in;
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wire [39:0] deser_out;
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periphery_clk_buf rx_clk_buf(
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.inclk (rx_dclk_in_p_dclk_in),
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.outclk (rx_clk)
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);
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assign gpio_in = {rx_strobe_in_p_strobe_in,
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rx_qdata_in_p_qdata3,
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rx_qdata_in_n_qdata2,
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rx_idata_in_p_idata1,
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rx_idata_in_n_idata0};
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assign {adc_data_strobe,
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adc_data_3,
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adc_data_2,
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adc_data_1,
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adc_data_0} = deser_out;
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genvar i;
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generate
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for (i = 0; i <= 4; i = i + 1) begin: g_ddr_i
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reg [7:0] shift_reg = 8'b0;
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wire [1:0] gpio_out;
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// DDR input
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adrv9001_gpio_in gpio_rx_in (
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.ck (rx_clk),
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.dout (gpio_out),
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.pad_in (gpio_in[i])
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);
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// Temporal ordering:
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// MSB - oldest received bit;
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// LSB - newest received bit;
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always @(posedge rx_clk) begin
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shift_reg <= {shift_reg[5:0],gpio_out[0],gpio_out[1]};
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end
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assign deser_out[i*8+:8] = shift_reg;
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end
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endgenerate
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always @(posedge rx_clk) begin
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if (adc_rst) begin
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valid_gen <= 4'b0001;
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end else begin
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valid_gen <= {valid_gen[2:0],valid_gen[3]};
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end
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end
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assign adc_valid = valid_gen[3];
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// No clock divider, qualifier used instead
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assign adc_clk_div = rx_clk;
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assign adc_clk = rx_clk;
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assign adc_clk_ratio = 1;
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// Drive unused signals
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assign delay_locked = 'b0;
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assign up_adc_drdata = 'b0;
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assign ssi_sync_out = 'b0;
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assign ssi_rst = 'b0;
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endmodule
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