Laszlo Nagy 71475e7dd8 jesd204: Expose core synthesis parameters through registers ... Make synthesis parameters accessible for the drivers. Rework implementation to reflect the parameters of the actual core and not of the AXI interfacing core.		2021-02-05 15:24:15 +02:00
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Makefile	axi_jesd204_common: Fix dependancies so that the IP can be generated Out Of Context	2019-03-21 15:36:57 +02:00
axi_jesd204_common_ip.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
jesd204_up_common.v	jesd204: Expose core synthesis parameters through registers	2021-02-05 15:24:15 +02:00
jesd204_up_sysref.v	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00