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bd
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jesd204: Xilinx: NP=12 support
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2021-02-05 15:24:15 +02:00 |
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Makefile
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jesd204: Add out of context constraint file for link layer cores
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2021-05-14 15:39:40 +03:00 |
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align_mux.v
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jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
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2021-02-05 15:24:15 +02:00 |
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elastic_buffer.v
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jesd204: Xilinx: NP=12 support
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2021-02-05 15:24:15 +02:00 |
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error_monitor.v
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jesd204_rx: 64b mode support for receive peripheral
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2020-02-10 09:47:07 +02:00 |
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jesd204_ilas_monitor.v
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jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
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2021-02-05 15:24:15 +02:00 |
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jesd204_lane_latency_monitor.v
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jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
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2021-02-05 15:24:15 +02:00 |
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jesd204_rx.v
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jesd20r_rx/jesd204_tx: Support for F=64
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2021-07-27 11:31:19 +03:00 |
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jesd204_rx_cgs.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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jesd204_rx_constr.sdc
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jesd204: Intel: NP12 support
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2021-02-05 15:24:15 +02:00 |
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jesd204_rx_constr.ttcl
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jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg
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2021-03-22 10:55:00 +02:00 |
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jesd204_rx_ctrl.v
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jesd204: Add support for 8-byte JESD204B, frame alignment character insertion/replacement
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2021-02-05 15:24:15 +02:00 |
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jesd204_rx_ctrl_64b.v
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jesd204_rx:jesd204_rx_ctrl_64b: Improve timing closure
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2021-03-08 10:46:52 +02:00 |
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jesd204_rx_frame_align.v
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jesd204: Xilinx: NP=12 support
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2021-02-05 15:24:15 +02:00 |
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jesd204_rx_header.v
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jesd204_rx: 64b mode support for receive peripheral
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2020-02-10 09:47:07 +02:00 |
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jesd204_rx_hw.tcl
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adi_jesd204: Add support of 16 lanes
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2021-07-27 10:28:48 +03:00 |
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jesd204_rx_ip.tcl
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jesd204: Add out of context constraint file for link layer cores
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2021-05-14 15:39:40 +03:00 |
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jesd204_rx_lane.v
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jesd204: Xilinx: NP=12 support
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2021-02-05 15:24:15 +02:00 |
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jesd204_rx_lane_64b.v
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jesd204_rx:64b: Remove reset
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2021-03-08 10:46:52 +02:00 |
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jesd204_rx_ooc.ttcl
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jesd204: Add out of context constraint file for link layer cores
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2021-05-14 15:39:40 +03:00 |
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