185 lines
6.1 KiB
Verilog
185 lines
6.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adxcvr_up #(
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// parameters
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parameter integer ID = 0,
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parameter integer TX_OR_RX_N = 0,
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parameter integer NUM_OF_LANES = 4) (
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// xcvr, lane-pll and ref-pll are shared
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output up_rst,
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input up_pll_locked,
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input [(NUM_OF_LANES-1):0] up_ready,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [ 9:0] up_waddr,
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input [31:0] up_wdata,
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output up_wack,
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input up_rreq,
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input [ 9:0] up_raddr,
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output [31:0] up_rdata,
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output up_rack);
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// parameters
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localparam [31:0] VERSION = 32'h00100161;
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// internal registers
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reg up_wreq_d = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_resetn = 'd0;
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reg [ 3:0] up_rst_cnt = 'd8;
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reg up_status_int = 'd0;
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reg up_rreq_d = 'd0;
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reg [31:0] up_rdata_d = 'd0;
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// internal signals
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wire up_ready_s;
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wire [31:0] up_status_32_s;
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wire [31:0] up_rparam_s;
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// defaults
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assign up_wack = up_wreq_d;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wreq_d <= 'd0;
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up_scratch <= 'd0;
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end else begin
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up_wreq_d <= up_wreq;
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if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin
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up_scratch <= up_wdata;
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end
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end
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end
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// reset-controller
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_resetn <= 'd0;
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end else begin
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if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin
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up_resetn <= up_wdata[0];
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end
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end
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end
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assign up_rst = up_rst_cnt[3];
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assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1];
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assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0;
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assign up_status_32_s[NUM_OF_LANES] = up_pll_locked;
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assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rst_cnt <= 4'h8;
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up_status_int <= 1'b0;
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end else begin
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if (up_resetn == 1'b0) begin
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up_rst_cnt <= 4'h8;
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end else if (up_rst_cnt[3] == 1'b1) begin
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up_rst_cnt <= up_rst_cnt + 1'b1;
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end
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if (up_resetn == 1'b0) begin
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up_status_int <= 1'b0;
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end else if (up_ready_s == 1'b1) begin
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up_status_int <= 1'b1;
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end
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end
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end
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// altera specific
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assign up_rparam_s[31:24] = 8'd0;
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// xilinx specific
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assign up_rparam_s[23:16] = 8'd0;
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// generic
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assign up_rparam_s[15: 9] = 7'd0;
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assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1;
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assign up_rparam_s[ 7: 0] = NUM_OF_LANES;
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// read interface
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assign up_rack = up_rreq_d;
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assign up_rdata = up_rdata_d;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rreq_d <= 'd0;
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up_rdata_d <= 'd0;
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end else begin
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up_rreq_d <= up_rreq;
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if (up_rreq == 1'b1) begin
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case (up_raddr)
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10'h000: up_rdata_d <= VERSION;
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10'h001: up_rdata_d <= ID;
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10'h002: up_rdata_d <= up_scratch;
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10'h004: up_rdata_d <= {31'd0, up_resetn};
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10'h005: up_rdata_d <= {31'd0, up_status_int};
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10'h006: up_rdata_d <= up_status_32_s;
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10'h009: up_rdata_d <= up_rparam_s;
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default: up_rdata_d <= 32'd0;
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endcase
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end else begin
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up_rdata_d <= 32'd0;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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