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pluto_hdl_adi/library/common
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Lars-Peter Clausen 9550c7f352 up_axi: Allow to configure AXI address width 
Not all peripherals need the full address space. To be able to infer the
size of the address space of a peripheral allow the size of the AXI address
signals to be configurable rather than hardcoding its width to 32 bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2017-04-18 12:17:40 +02:00
..
ad_addsub.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_axi_ip_constr.sdc library- altera power up warnings 2016-12-20 16:18:15 -05:00
ad_axis_inf_rx.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_csc_1.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_csc_1_add.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_csc_1_mul.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_csc_CrYCb2RGB.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_csc_RGB2CrYCb.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_datafmt.v common- adc- data path disable split 2016-09-23 13:40:35 -04:00
ad_dcfilter.v common- adc- data path disable split 2016-09-23 13:40:35 -04:00
ad_dds.v common- dac data path split 2016-09-23 16:13:24 -04:00
ad_dds_1.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_dds_sine.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_edge_detect.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_gt_channel.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_gt_channel_1.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_gt_common.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_gt_common_1.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_gt_es.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_gt_es_axi.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_iqcor.v common- adc- data path disable split 2016-09-23 13:40:35 -04:00
ad_jesd_align.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_mem.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_mem_asym.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_pnmon.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_rst.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_ss_422to444.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_ss_444to422.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_sysref_gen.v ad_sysref_gen: Fix sysref generation 2016-12-19 18:02:49 +02:00
ad_tdd_control.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
ad_xcvr_rx_if.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
axi_ctrlif.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
axi_streaming_dma_rx_fifo.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
axi_streaming_dma_tx_fifo.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
dma_fifo.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
pl330_dma_fifo.vhd Add .gitattributes file 2015-06-26 11:07:10 +02:00
sync_bits.v all: Change tab to double space 2016-10-01 18:13:42 +03:00
sync_gray.v all: Change tab to double space 2016-10-01 18:13:42 +03:00
up_adc_channel.v common- adc- data path disable split 2016-09-23 13:40:35 -04:00
up_adc_common.v up_adc_common: Added clock enable control for the ADC cores 2017-04-18 12:17:40 +02:00
up_axi.v up_axi: Allow to configure AXI address width 2017-04-18 12:17:40 +02:00
up_clkgen.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_clock_mon.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_dac_channel.v common- dac data path split 2016-09-23 16:13:24 -04:00
up_dac_common.v up_dac_common: Added clock enable control for the DAC cores 2017-04-18 12:17:40 +02:00
up_delay_cntrl.v axi_ad9361- add receive init delay 2017-03-13 16:28:24 -04:00
up_gt.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_gt_channel.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_hdmi_rx.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_hdmi_tx.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_pmod.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_tdd_cntrl.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_xfer_cntrl.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
up_xfer_status.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
util_pulse_gen.v all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00