449 lines
17 KiB
Verilog
449 lines
17 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_tdd_cntrl #(
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parameter ID = 0) (
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input clk,
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input rst,
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//rf tdd interface control
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output tdd_enable,
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output tdd_secondary,
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output tdd_rx_only,
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output tdd_tx_only,
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output tdd_gated_rx_dmapath,
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output tdd_gated_tx_dmapath,
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output [ 7:0] tdd_burst_count,
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output [23:0] tdd_counter_init,
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output [23:0] tdd_frame_length,
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output tdd_terminal_type,
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output [23:0] tdd_vco_rx_on_1,
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output [23:0] tdd_vco_rx_off_1,
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output [23:0] tdd_vco_tx_on_1,
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output [23:0] tdd_vco_tx_off_1,
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output [23:0] tdd_rx_on_1,
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output [23:0] tdd_rx_off_1,
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output [23:0] tdd_rx_dp_on_1,
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output [23:0] tdd_rx_dp_off_1,
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output [23:0] tdd_tx_on_1,
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output [23:0] tdd_tx_off_1,
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output [23:0] tdd_tx_dp_on_1,
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output [23:0] tdd_tx_dp_off_1,
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output [23:0] tdd_vco_rx_on_2,
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output [23:0] tdd_vco_rx_off_2,
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output [23:0] tdd_vco_tx_on_2,
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output [23:0] tdd_vco_tx_off_2,
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output [23:0] tdd_rx_on_2,
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output [23:0] tdd_rx_off_2,
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output [23:0] tdd_rx_dp_on_2,
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output [23:0] tdd_rx_dp_off_2,
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output [23:0] tdd_tx_on_2,
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output [23:0] tdd_tx_off_2,
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output [23:0] tdd_tx_dp_on_2,
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output [23:0] tdd_tx_dp_off_2,
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input [ 7:0] tdd_status,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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localparam PCORE_VERSION = 32'h00010061;
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// internal registers
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reg [31:0] up_scratch = 32'h0;
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reg up_tdd_enable = 1'h0;
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reg up_tdd_secondary = 1'h0;
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reg up_tdd_rx_only = 1'h0;
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reg up_tdd_tx_only = 1'h0;
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reg up_tdd_gated_tx_dmapath = 1'h0;
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reg up_tdd_gated_rx_dmapath = 1'h0;
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reg up_tdd_terminal_type = 1'h0;
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reg [ 7:0] up_tdd_burst_count = 8'h0;
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reg [23:0] up_tdd_counter_init = 24'h0;
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reg [23:0] up_tdd_frame_length = 24'h0;
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reg [23:0] up_tdd_vco_rx_on_1 = 24'h0;
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reg [23:0] up_tdd_vco_rx_off_1 = 24'h0;
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reg [23:0] up_tdd_vco_tx_on_1 = 24'h0;
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reg [23:0] up_tdd_vco_tx_off_1 = 24'h0;
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reg [23:0] up_tdd_rx_on_1 = 24'h0;
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reg [23:0] up_tdd_rx_off_1 = 24'h0;
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reg [23:0] up_tdd_rx_dp_on_1 = 24'h0;
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reg [23:0] up_tdd_rx_dp_off_1 = 24'h0;
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reg [23:0] up_tdd_tx_on_1 = 24'h0;
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reg [23:0] up_tdd_tx_off_1 = 24'h0;
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reg [23:0] up_tdd_tx_dp_on_1 = 24'h0;
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reg [23:0] up_tdd_tx_dp_off_1 = 24'h0;
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reg [23:0] up_tdd_vco_rx_on_2 = 24'h0;
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reg [23:0] up_tdd_vco_rx_off_2 = 24'h0;
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reg [23:0] up_tdd_vco_tx_on_2 = 24'h0;
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reg [23:0] up_tdd_vco_tx_off_2 = 24'h0;
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reg [23:0] up_tdd_rx_on_2 = 24'h0;
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reg [23:0] up_tdd_rx_off_2 = 24'h0;
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reg [23:0] up_tdd_rx_dp_on_2 = 24'h0;
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reg [23:0] up_tdd_rx_dp_off_2 = 24'h0;
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reg [23:0] up_tdd_tx_on_2 = 24'h0;
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reg [23:0] up_tdd_tx_off_2 = 24'h0;
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reg [23:0] up_tdd_tx_dp_on_2 = 24'h0;
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reg [23:0] up_tdd_tx_dp_off_2 = 24'h0;
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// internal signals
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wire up_wreq_s;
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wire up_rreq_s;
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wire [ 7:0] up_tdd_status_s;
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// decode block select
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assign up_wreq_s = (up_waddr[13:8] == 6'h20) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:8] == 6'h20) ? up_rreq : 1'b0;
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// processor write interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 1'h0;
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up_scratch <= 32'h0;
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up_tdd_enable <= 1'h0;
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up_tdd_secondary <= 1'h0;
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up_tdd_rx_only <= 1'h0;
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up_tdd_tx_only <= 1'h0;
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up_tdd_gated_tx_dmapath <= 1'h0;
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up_tdd_gated_rx_dmapath <= 1'h0;
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up_tdd_terminal_type <= 1'h0;
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up_tdd_counter_init <= 24'h0;
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up_tdd_frame_length <= 24'h0;
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up_tdd_burst_count <= 8'h0;
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up_tdd_vco_rx_on_1 <= 24'h0;
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up_tdd_vco_rx_off_1 <= 24'h0;
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up_tdd_vco_tx_on_1 <= 24'h0;
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up_tdd_vco_tx_off_1 <= 24'h0;
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up_tdd_rx_on_1 <= 24'h0;
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up_tdd_rx_off_1 <= 24'h0;
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up_tdd_rx_dp_on_1 <= 24'h0;
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up_tdd_rx_dp_off_1 <= 24'h0;
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up_tdd_tx_on_1 <= 24'h0;
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up_tdd_tx_off_1 <= 24'h0;
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up_tdd_tx_dp_on_1 <= 24'h0;
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up_tdd_tx_dp_off_1 <= 24'h0;
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up_tdd_vco_rx_on_2 <= 24'h0;
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up_tdd_vco_rx_off_2 <= 24'h0;
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up_tdd_vco_tx_on_2 <= 24'h0;
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up_tdd_vco_tx_off_2 <= 24'h0;
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up_tdd_rx_on_2 <= 24'h0;
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up_tdd_rx_off_2 <= 24'h0;
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up_tdd_rx_dp_on_2 <= 24'h0;
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up_tdd_rx_dp_off_2 <= 24'h0;
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up_tdd_tx_on_2 <= 24'h0;
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up_tdd_tx_off_2 <= 24'h0;
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up_tdd_tx_dp_on_2 <= 24'h0;
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up_tdd_tx_dp_off_2 <= 24'h0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
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up_tdd_enable <= up_wdata[0];
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up_tdd_secondary <= up_wdata[1];
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up_tdd_rx_only <= up_wdata[2];
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up_tdd_tx_only <= up_wdata[3];
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up_tdd_gated_rx_dmapath <= up_wdata[4];
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up_tdd_gated_tx_dmapath <= up_wdata[5];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
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up_tdd_burst_count <= up_wdata[7:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
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up_tdd_counter_init <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
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up_tdd_frame_length <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
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up_tdd_terminal_type <= up_wdata[0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
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up_tdd_vco_rx_on_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
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up_tdd_vco_rx_off_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
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up_tdd_vco_tx_on_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin
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up_tdd_vco_tx_off_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin
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up_tdd_rx_on_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin
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up_tdd_rx_off_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin
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up_tdd_tx_on_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin
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up_tdd_tx_off_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
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up_tdd_rx_dp_on_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
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up_tdd_rx_dp_off_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin
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up_tdd_tx_dp_on_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin
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up_tdd_tx_dp_off_1 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin
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up_tdd_vco_rx_on_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin
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up_tdd_vco_rx_off_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin
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up_tdd_vco_tx_on_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin
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up_tdd_vco_tx_off_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin
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up_tdd_rx_on_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin
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up_tdd_rx_off_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin
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up_tdd_tx_on_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin
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up_tdd_tx_off_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin
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up_tdd_rx_dp_on_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin
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up_tdd_rx_dp_off_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin
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up_tdd_tx_dp_on_2 <= up_wdata[23:0];
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3b)) begin
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up_tdd_tx_dp_off_2 <= up_wdata[23:0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 1'b0;
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up_rdata <= 1'b0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[7:0])
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8'h00: up_rdata <= PCORE_VERSION;
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8'h01: up_rdata <= ID;
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8'h02: up_rdata <= up_scratch;
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8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath,
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up_tdd_gated_rx_dmapath,
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up_tdd_tx_only,
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up_tdd_rx_only,
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up_tdd_secondary,
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up_tdd_enable};
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8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
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8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
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8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
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8'h14: up_rdata <= {31'h0, up_tdd_terminal_type};
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8'h18: up_rdata <= {24'h0, up_tdd_status_s};
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8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
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8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
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8'h22: up_rdata <= { 8'h0, up_tdd_vco_tx_on_1};
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8'h23: up_rdata <= { 8'h0, up_tdd_vco_tx_off_1};
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8'h24: up_rdata <= { 8'h0, up_tdd_rx_on_1};
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8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1};
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8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1};
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8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1};
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8'h28: up_rdata <= { 8'h0, up_tdd_rx_dp_on_1};
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8'h29: up_rdata <= { 8'h0, up_tdd_rx_dp_off_1};
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8'h2a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1};
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8'h2b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1};
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8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2};
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8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2};
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8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2};
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8'h33: up_rdata <= { 8'h0, up_tdd_vco_tx_off_2};
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8'h34: up_rdata <= { 8'h0, up_tdd_rx_on_2};
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8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2};
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8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2};
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8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2};
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8'h38: up_rdata <= { 8'h0, up_tdd_rx_dp_on_2};
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8'h39: up_rdata <= { 8'h0, up_tdd_rx_dp_off_2};
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8'h3a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2};
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8'h3b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2};
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default: up_rdata <= 32'h0;
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endcase
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end
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end
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end
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// rf tdd control signal CDC
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up_xfer_cntrl #(.DATA_WIDTH(15)) i_xfer_tdd_control (
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_data_cntrl({up_tdd_enable,
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up_tdd_secondary,
|
|
up_tdd_rx_only,
|
|
up_tdd_tx_only,
|
|
up_tdd_gated_rx_dmapath,
|
|
up_tdd_gated_tx_dmapath,
|
|
up_tdd_burst_count,
|
|
up_tdd_terminal_type
|
|
}),
|
|
.up_xfer_done(),
|
|
.d_rst(rst),
|
|
.d_clk(clk),
|
|
.d_data_cntrl({tdd_enable,
|
|
tdd_secondary,
|
|
tdd_rx_only,
|
|
tdd_tx_only,
|
|
tdd_gated_rx_dmapath,
|
|
tdd_gated_tx_dmapath,
|
|
tdd_burst_count,
|
|
tdd_terminal_type
|
|
}));
|
|
|
|
up_xfer_cntrl #(.DATA_WIDTH(624)) i_xfer_tdd_counter_values (
|
|
.up_rstn(up_rstn),
|
|
.up_clk(up_clk),
|
|
.up_data_cntrl({up_tdd_counter_init,
|
|
up_tdd_frame_length,
|
|
up_tdd_vco_rx_on_1,
|
|
up_tdd_vco_rx_off_1,
|
|
up_tdd_vco_tx_on_1,
|
|
up_tdd_vco_tx_off_1,
|
|
up_tdd_rx_on_1,
|
|
up_tdd_rx_off_1,
|
|
up_tdd_tx_on_1,
|
|
up_tdd_tx_off_1,
|
|
up_tdd_rx_dp_on_1,
|
|
up_tdd_rx_dp_off_1,
|
|
up_tdd_tx_dp_on_1,
|
|
up_tdd_tx_dp_off_1,
|
|
up_tdd_vco_rx_on_2,
|
|
up_tdd_vco_rx_off_2,
|
|
up_tdd_vco_tx_on_2,
|
|
up_tdd_vco_tx_off_2,
|
|
up_tdd_rx_on_2,
|
|
up_tdd_rx_off_2,
|
|
up_tdd_tx_on_2,
|
|
up_tdd_tx_off_2,
|
|
up_tdd_rx_dp_on_2,
|
|
up_tdd_rx_dp_off_2,
|
|
up_tdd_tx_dp_on_2,
|
|
up_tdd_tx_dp_off_2
|
|
}),
|
|
.up_xfer_done(),
|
|
.d_rst(rst),
|
|
.d_clk(clk),
|
|
.d_data_cntrl({tdd_counter_init,
|
|
tdd_frame_length,
|
|
tdd_vco_rx_on_1,
|
|
tdd_vco_rx_off_1,
|
|
tdd_vco_tx_on_1,
|
|
tdd_vco_tx_off_1,
|
|
tdd_rx_on_1,
|
|
tdd_rx_off_1,
|
|
tdd_tx_on_1,
|
|
tdd_tx_off_1,
|
|
tdd_rx_dp_on_1,
|
|
tdd_rx_dp_off_1,
|
|
tdd_tx_dp_on_1,
|
|
tdd_tx_dp_off_1,
|
|
tdd_vco_rx_on_2,
|
|
tdd_vco_rx_off_2,
|
|
tdd_vco_tx_on_2,
|
|
tdd_vco_tx_off_2,
|
|
tdd_rx_on_2,
|
|
tdd_rx_off_2,
|
|
tdd_tx_on_2,
|
|
tdd_tx_off_2,
|
|
tdd_rx_dp_on_2,
|
|
tdd_rx_dp_off_2,
|
|
tdd_tx_dp_on_2,
|
|
tdd_tx_dp_off_2
|
|
}));
|
|
|
|
up_xfer_status #(.DATA_WIDTH(8)) i_xfer_tdd_status (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_data_status (up_tdd_status_s),
|
|
.d_rst (rst),
|
|
.d_clk (clk),
|
|
.d_data_status (tdd_status));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|