1022 lines
47 KiB
ReStructuredText
1022 lines
47 KiB
ReStructuredText
.. _axi_jesd204_tx:
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JESD204B/C Link Transmit Peripheral
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================================================================================
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.. hdl-component-diagram::
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The Analog Devices JESD204B/C Link Transmit Peripheral implements the link layer
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handling of a JESD204 transmit logic device. Implements the 8B/10B based link
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layer defined in JESD204C standard that is similar to the link layer defined in
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JESD204B. This includes handling of the SYSREF and SYNC~ and controlling the
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:ref:`link state machine <axi_jesd204_tx_8b_10b_link_state_machine>` accordingly
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as well as performing per lane scrambling and character replacement. It has
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been designed for interoperability with
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:ref:`Analog Devices JESD204B DAC converter products <axi_jesd204_tx_supported_devices>`.
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Implements the 64B/66B based link layer defined in the JESD204C standard.
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This includes handling of the SYSREF, per lane encoding of sync header,
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scrambling as per data multi-block CRC generation.
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The type of link layer is selectable during implementation phase through the
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``LINK_MODE`` synthesis parameter.
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To form a complete JESD204 transmit logic device it has to be combined with a
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:ref:`PHY layer <jesd204_physical_layer>` and
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:ref:`transport layer <jesd204_transport_layer>` peripheral.
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Features
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--------------------------------------------------------------------------------
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* Backwards compatibility with JESD204B;
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* 64B/66B link layer defined in JESD204C;
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* Subclass 0 and Subclass 1 support;
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* Deterministic Latency (for Subclass 1 operation);
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* Runtime re-configurability through memory-mapped register interface (AXI4);
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* Interrupts for event notification;
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* Diagnostics;
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* Max Lanerate with 8B/10B mode: 15 Gbps;
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* Max Lanerate with 64B/66B mode: 32 Gbps;
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* Low Latency;
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* Independent per lane enable/disable.
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..
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Utilization
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--------------------------------------------------------------------------------
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.. collapsible:: Detailed Utilization
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+---------------+---------+----+---+
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|Device Family |NUM_LANES|LUTs|FFs|
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+===============+=========+====+===+
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|Intel Arria 10 |1 |TBD |TDB|
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+ +---------+----+---+
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| |2 |TBD |TBD|
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+ +---------+----+---+
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| |4 |TBD |TBD|
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+ +---------+----+---+
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| |8 |TBD |TBD|
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+---------------+---------+----+---+
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|AMD Xilinx |1 |TBD |TBD|
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|Artix 7 +---------+----+---+
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| |2 |TBD |TBD|
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+ +---------+----+---+
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| |4 |TBD |TBD|
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+ +---------+----+---+
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| |8 |TBD |TBD|
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+---------------+---------+----+---+
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|AMD Xilinx |1 |TBD |TBD|
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|Kintex 7 +---------+----+---+
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| |2 |TBD |TBD|
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+ +---------+----+---+
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| |4 |824 |897|
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+ +---------+----+---+
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| |8 |TBD |TBD|
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+---------------+---------+----+---+
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|AMD Xilinx |1 |TBD |TBD|
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|Virtex 7 +---------+----+---+
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| |2 |TBD |TBD|
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+ +---------+----+---+
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| |4 |TBD |TBD|
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+ +---------+----+---+
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| |8 |TBD |TBD|
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+---------------+---------+----+---+
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Files
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--------------------------------------------------------------------------------
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.. list-table::
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:header-rows: 1
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* - Name
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- Description
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* - :git-hdl:`axi_jesd204_tx.v <library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v>`
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- Verilog source for the peripheral.
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* - :git-hdl:`axi_jesd204_tx_ip.tcl <library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl>`
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- TCL script to generate the Vivado IP-integrator project for the
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peripheral.
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Block Diagram
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--------------------------------------------------------------------------------
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.. image:: axi_jesd204_tx_204c.svg
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:align: center
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AXI JESD204 TX Synthesis Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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* - ID
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- Instance identification number.
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* - NUM_LANES
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- Maximum number of lanes supported by the peripheral.
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* - NUM_LINKS
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- Maximum number of links supported by the peripheral.
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* - LINK_MODE
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- | Decoder selection of the link layer.
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| 1 - 8B/10B mode;
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| 2 - 64B/66B mode.
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* - DATA_PATH_WIDTH
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- Data path width in bytes. Set it 4 in case of 8B/10B, 8 in case of
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64B/66B.
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JESD204 TX Synthesis Configuration Parameters
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--------------------------------------------------------------------------------
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.. hdl-parameters::
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:path: library/jesd204/jesd204_tx
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* - NUM_LANES
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- Maximum number of lanes supported by the peripheral.
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* - NUM_LINKS
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- Maximum number of links supported by the peripheral.
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* - LINK_MODE
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- | Decoder selection of the link layer.
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| 1 - 8B/10B mode;
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| 2 - 64B/66B mode.
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* - DATA_PATH_WIDTH
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- Data path width in bytes. Set it to 4 in case of 8B/10B, 8 in case of
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64B/66B.
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* - TPL_DATA_PATH_WIDTH
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- Data path width in bytes towards transport layer. Must be greater or
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equal to ``DATA_PATH_WIDTH``. Must be a power of 2 integer multiple of
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the F parameter.
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* - ASYNC_CLK
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- Set this parameter to 1 if the link clock and the device clocks have
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different frequencies, or if they have the same frequency but a
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different source. If set, synchronizing logic and a gearbox of ratio
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``DATA_PATH_WIDTH``:``TPL_DATA_PATH_WIDTH`` is inserted to do the rate
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conversion. If not set, ``TPL_DATA_PATH_WIDTH`` must match
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``DATA_PATH_WIDTH``, the same clock must be connected to ``clk`` and
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``device_clk`` inputs.
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AXI JESD204 TX Signal and Interface Pins
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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* - s_axi_aclk
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- All ``S_AXI`` signals and ``irq`` are synchronous to this clock.
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* - s_axi_aresetn
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- Resets the internal state of the peripheral.
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* - s_axi
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- Memory mapped AXI-lite bus that provides access to modules register map.
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* - irq
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- Interrupt output of the module. Is asserted when at least one of the
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modules interrupt is pending and enabled.
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* - device_clk
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- :dokuwiki:`Device clock <resources/fpga/peripherals/jesd204/jesd204_glossary#clocks>`
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for the JESD204 interface. Its frequency must be link clock \* ``DATA_PATH_WIDTH`` /
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``TPL_DATA_PATH_WIDTH``
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* - device_reset
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- Reset active high synchronous with the
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:dokuwiki:`Device clock <resources/fpga/peripherals/jesd204/jesd204_glossary#clocks>`.
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JESD204 TX Signal and Interface Pins
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--------------------------------------------------------------------------------
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.. hdl-interfaces::
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:path: library/jesd204/jesd204_tx
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* - clk
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- :dokuwiki:`Link clock <resources/fpga/peripherals/jesd204/jesd204_glossary#clocks>`
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for the JESD204 interface. Must be line clock/40 for correct
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operation in 8B/10B mode, line clock/66 in 64B/66B mode.
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* - reset
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- Reset active high synchronous with the
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:dokuwiki:`Link clock <resources/fpga/peripherals/jesd204/jesd204_glossary#clocks>`.
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* - tx_data
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- Transmit data.
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* - sync
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- sync[m-1:0] is JESD204B SYNC~ (or SYNC_N) signal, available in 8B/10B mode.
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(``0 <= n < NUM_LINKS``)
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* - sysref
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- JESD204 SYSREF signal.
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* - tx_phy*
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- n-th lane of the JESD204 interface (``0 <= n < NUM_LANES``).
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Register Map
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--------------------------------------------------------------------------------
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.. hdl-regmap::
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:name: JESD_TX
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:no-type-info:
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Theory of Operation
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--------------------------------------------------------------------------------
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The JESD204B/C transmit peripheral consists of two main components. The register
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map and the link processor. Both components are fully asynchronous and are
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clocked by independent clocks. The register map is in the ``s_axi_aclk`` clock
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domain, while the link processor is in the ``clk`` and ``device_clk`` clock
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domain.
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The register map is used to configure the operational parameters of the link
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processor as well as to query the current state of the link processor. The link
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processor itself is responsible for handling the JESD204 link layer protocol.
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Interfaces and Signals
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Register Map Configuration Interface
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The register map configuration interface can be accessed through the AXI4-Lite
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``S_AXI`` interface. The interface is synchronous to the ``s_axi_aclk``. The
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``s_axi_aresetn`` signal is used to reset the peripheral and should be asserted
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during system startup until the ``s_axi_aclk`` is active and stable.
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De-assertion of the reset signal should by synchronous to ``s_axi_aclk``.
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JESD204B Control Signals
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The ``sync`` and ``sysref`` signals corresponds to the SYNC~ and SYSREF signals
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of the JESD204 specification. These are signals generated externally and need to
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be connected to the peripheral for correct operation.
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In 8B/10B link layer the ``sysref`` signal is optional and only required to
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achieve deterministic latency in subclass 1 mode operation. If the ``sysref``
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signal is not connected software needs to configure the peripheral accordingly
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to indicate this. In 64B/66B link layer the ``sysref`` signal is mandatory.
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When the ``sysref`` signal is used, in order to ensure correct operation, it is
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important that setup and hold of the external signal relative to the
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``device_clk`` signal are met. Otherwise deterministic latency can not be
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guaranteed.
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Transceiver Interface (TX_PHYn)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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For each lane the peripheral has one corresponding ``TX_PHY`` interface. These
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interfaces provide the pre-processed physical layer data. The TX_PHY interfaces
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should be connected to the down-stream physical layer transceiver peripheral.
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The physical layer peripheral receiving data from these interfaces are
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responsible for performing the final 8b10b mapping as well as serializing the
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data and transmitting it on the physical CML differential high-speed serial
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lane.
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.. _axi_jesd204_tx_user_data:
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User Data Interface (TX_DATA)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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User data is accepted on the the AXI4-Stream ``TX_DATA`` interface. The
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interface is a reduced AXI4-Stream interface and only features the TREADY flow
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control signal, but not the TVALID flow control signal. The behavior of the
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interface is as if the TVALID signal was always asserted. This means as soon as
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tx_ready is asserted a continuous stream of user data must be provided on
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tx_data.
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.. wavedrom::
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:align: center
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{signal:
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[
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['TX_DATA',
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{ name: "device_clk", wave: 'P.........' },
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{ name: "tx_data", wave: "x...======",
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data: ["D0", "D1", "D2", "D3", "D4", "..."] },
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{ name: 'tx_ready', wave: '0...1.....' },
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]
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],
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foot:
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{text:
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['tspan',{dx:'-45'}, 'Link Inicialization', ['tspan', {dx:'60'},
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'User Data Phase'],],
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}
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}
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After reset and during link initialization the ``tx_ready`` signal is
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de-asserted. As soon as the :ref:`User Data Phase <axi_jesd204_tx_user_data_phase>` is
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entered the ``tx_ready`` will be asserted to indicate that the peripheral is now
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accepting and processing the data from the ``tx_data`` signal. The ``tx_ready``
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signal stays asserted until the link is either deactivated or re-initialized.
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.. image:: octets_mapping.svg
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:align: right
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Typically the ``TX_DATA`` interface is connected to a JESD204B transport layer
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peripheral that provides framed and lane mapped data. The internal data path
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width of the peripheral is four, this means that four octets per lane are
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processed in parallel. When in the user data phase the peripheral expects to
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receive data for four octets for each lane in each beat.
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This means that ``TX_DATA`` interface is ``DATA_PATH_WIDTH`` \* 8 \*
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``NUM_LANES`` bits wide. With each block of consecutive ``DATA_PATH_WIDTH`` \*
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8 bits corresponding to one lane. The lowest ``DATA_PATH_WIDTH`` \* 8 bits
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correspond to the first lane, while the highest ``DATA_PATH_WIDTH`` \* 8 bits
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correspond to the last lane.
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E.g. for 8B/10B mode where DATA_PATH_WIDTH=4. Each lane specific 32-bit block
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corresponds to four octets each 8 bits wide. The temporal ordering of the
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octets is from LSB to MSB, this means the octet placed in the lowest 8 bits is
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transmitted first, the octet placed in the highest 8 bits is transmitted last.
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Data corresponding to lanes that have been disabled are ignored and their value
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is don't care.
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Configuration Interface
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The peripheral features a register map configuration interface that can be
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accessed through the AXI4-Lite ``S_AXI`` port. The register map can be used to
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configure the peripherals operational parameters, query the current status of
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the device and query the features supported by the device.
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Peripheral Identification and HDL Synthesis Settings
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The peripheral contains multiple registers that allow the identification of the
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peripheral as well as the discovery of features that were configured at HDL
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synthesis time. Apart from the ``SCRATCH`` register all registers in this
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section are read-only and write to them will be ignored.
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The ``VERSION`` (``0x000``) register contains the version of the peripheral. The
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version determines the register map layout and general features supported by the
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peripheral. The version number follows `semantic versioning <http://semver.org/>`__.
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Increments in the major number indicate backward incompatible changes,
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increments in the minor number indicate backward compatible changes, patch
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letter increments indicate a bug fix.
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The ``PERIPHERAL_ID`` (``0x004``) register contains the value of the ``ID`` HDL
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configuration parameter that was set during synthesis. Its primary function is
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to allow to distinguish between multiple instances of the peripheral in the same
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design.
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The ``SCRATCH`` (``0x008``) register is a general purpose 32-bit register that
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can be set to an arbitrary values. Reading the register will yield the value
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previously written (The value will be cleared when the peripheral is reset). Its
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content does not affect the operation of the peripheral. It can be used by
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software to test whether the register map is accessible or store custom
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peripheral associated data.
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The ``IDENTIFICATION`` (``0x00c``) register contains the value of ``"204T"``.
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This value is unique to this type of peripheral and can be used to ensure that
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the peripheral exists at the expected location in the memory mapped IO register
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space.
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The ``SYNTH_NUM_LANES`` (``0x010``) register contains the value of the
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``NUM_LANES`` HDL configuration parameter that was set during synthesis. It
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corresponds to the maximum of lanes supported by the peripheral. Possible values
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are between ``1`` and ``32``.
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The ``SYNTH_DATA_PATH_WIDTH`` (``0x014``) register contains the value of the
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internal data path width per lane in octets. This is how many octets are
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processed in parallel on each lane and affects the restrictions of possible
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values for certain runtime configuration registers. The value is encoded as the
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log2() of the data path width. Possible values are:
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#. Internal data path width is 2;
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#. Internal data path width is 4;
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#. Internal data path width is 8.
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Interrupt Handling
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Interrupt processing is handled by three closely related registers. All three
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registers follow the same layout, each bit in the register corresponds to one
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particular interrupt.
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When an interrupt event occurs it is recorded in the ``IRQ_SOURCE`` (``0x088``)
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register. For a recorded interrupt event the corresponding bit is set to 1. If
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an interrupt event occurs while the bit is already set to 1 it will stay set to
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1.
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The ``IRQ_ENABLE`` (``0x080``) register controls how recorded interrupt events
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propagate. An interrupt is considered to be enabled if the corresponding bit in
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the ``IRQ_ENABLE`` register is set to 1, it is considered to be disabled if the
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bit is set to 0.
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Disabling an interrupt will not prevent it from being recorded, but only its
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propagation. This means if an interrupt event was previously recorded while the
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interrupt was disabled and the interrupt is being enabled the interrupt event
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will then propagate.
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An interrupt event that has been recorded and is enabled propagates to the
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``IRQ_PENDING`` (``0x084``) register. The corresponding bit for such an
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interrupt will read as 1. Disabled or interrupts for which no events have been
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recorded will read as 0. Also if at least one interrupt has been recorded and is
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enabled the external ``irq`` signal will be asserted to signal the IRQ event to
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the upstream IRQ controller.
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A recorded interrupt event can be cleared (or acknowledged) by writing a 1 to
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the corresponding bit to either the ``IRQ_SOURCE`` or ``IRQ_PENDING`` register.
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It is possible to clear multiple interrupt events at the same time by setting
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multiple bits in a single write operation.
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For more details regarding interrupt operation see the
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:ref:`interrupts section <axi_jesd204_tx_interrupts>` of this document.
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Link Control
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The ``LINK_DISABLE`` (``0x0c0``) register is used to control the link state and
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switch between enabled and disabled. While the link is disabled its state
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machine will remain in reset and it will not react to any external event like
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the ``SYSREF`` or ``SYNC~`` signals.
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Writing a 0 to the ``LINK_DISABLE`` register will enable the link. While the
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link state is changing from disabled to enabled it will go through a short
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initialization procedure, which will take a few clock cycles. To check whether
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the initialization procedure has completed and the link is fully operational the
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``LINK_STATE`` (``0x0c4``) register can be checked. This register will contain a
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0 when the link is fully enabled and will contain a 1 while it is disabled or
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going through the initialization procedure.
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Writing a 1 to the ``LINK_DISABLE`` register will immediately disable the link.
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The ``EXTERNAL_RESET`` (``[1]``) bit in the ``LINK_STATE`` register indicates
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whether the external link reset signal is asserted (``1``) or de-asserted
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(``0``). When the external link reset is asserted the link is disabled
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regardless of the setting of ``LINK_DISABLE``. The external link reset is
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controlled by the fabric and might be asserted if the link clock is not stable
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yet.
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Multi-link Control
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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A multi-link is a link where multiple converter devices are connected to a
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single logic device (FPGA). All links involved in a multi-link are synchronous
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and established at the same time. For an 8B/10B TX link, this means that the
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FPGA receives multiple SYNC signals, one for each link.
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For a 8B/10B link the ``MULTI_LINK_DISABLE`` register allows activating or
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deactivating each ``SYNC~`` lines independently. This is useful when depending
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on the use case profile some converter devices are supposed to be disabled.
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Link Configuration
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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The link configuration registers control certain aspects of the runtime behavior
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of the peripheral. Since the JESD204 standard does now allow changes to link
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configuration while the link is active the link configuration registers can only
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be modified while the link is disabled. As soon as it is enabled the
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configuration registers turn read-only and any writes to them will be ignored.
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|
|
The ``LANES_DISABLE`` (``0x200``) register allows to disable individual lanes.
|
|
Each bit in the register corresponds to a particular lane and indicates whether
|
|
that lane is enabled or disabled. Bit 0 corresponds to the first lane, bit 1 to
|
|
the second lane and so on. A value of 0 for a specific bit means the
|
|
corresponding lane is enabled, a value of 1 means the lane is disabled. A
|
|
disabled lane will not transmit any data when the link is otherwise active. By
|
|
default, all lanes are enabled.
|
|
|
|
The ``LINK_CONF0`` register configures the octets-per-frame and
|
|
frames-per-multi-frame settings of the link. The ``OCTETS_PER_FRAME``
|
|
(``[18:16]``) field should be set to the number of octets-per-frame minus 1 (F -
|
|
1). The ``OCTETS_PER_MULTIFRAME`` (``[9:0]``) field should be set to the number
|
|
of octets-per-frame multiplied by the number of frames-per-multi-frame minus 1
|
|
(FxK - 1). For correct operation FxK must be a multiple of ``DATA_PATH_WIDTH``.
|
|
In 64B/66B mode this field matches and also represents the number of octets per
|
|
extended multiblock (Ex32x8 - 1).
|
|
|
|
The ``LINK_CONF1`` register controls the optional link level processing stages.
|
|
The ``SCRAMBLER_DISABLE`` (``[0]``) bit controls whether scrambling of the
|
|
transmitted user data is enabled or disabled. A value of 0 enables scrambling
|
|
and a value of 1 disables it. In 64B/66B mode scrambling must be always enabled.
|
|
The ``CHAR_REPLACEMENT_DISABLE`` (``[1]``) bit controls whether alignment
|
|
character replacement is performed or not. A value of 0 enables character
|
|
replacement and a value of 1 disables it. For correct operation, character
|
|
replacement must be disabled when scrambling is disabled otherwise undefined
|
|
behavior might occur.
|
|
|
|
Both the transmitter as well as receiver device on the JESD204 link need to be
|
|
configured with the same settings for scrambling/descrambling and character
|
|
replacement for correct operation.
|
|
|
|
It is recommended to leave both scrambling as well as alignment character
|
|
replacement enabled during normal operation and only disable it for debugging or
|
|
testing purposes.
|
|
|
|
Character replacement is used only in 8B/10B links and completely disregarded in
|
|
64B/66B mode.
|
|
|
|
The ``LINK_CONF2`` (``0x240``) register contains configuration data that affects
|
|
the transitions of the :ref:`link state machine <axi_jesd204_tx_8b_10b_link_state_machine>`. If the
|
|
``CONTINUOUS_CGS`` (``[0]``) bit is set the state machine will remain in the CGS
|
|
phase indefinitely and send repeated :dokuwiki:`/K/ control character
|
|
<resources/fpga/peripherals/jesd204/jesd204_glossary#control_characters>`.
|
|
If the ``CONTINUOUS_ILAS`` (``[1]``) bit is set the state machine will remain
|
|
in the ILAS phase indefinitely and send repeated ILAS sequences. If the
|
|
``SKIP_ILAS`` (``[2]``) bit is set the state machine will directly transition
|
|
to the DATA phase from the CGS phase without going through the ILAS phase.
|
|
The ``LINK_CONFIG2`` register is used only in 8B/10B links and completely
|
|
disregarded in 64B/66B mode.
|
|
|
|
The ``LINK_CONF3`` (``0x244``) register configures the duration of the ILAS
|
|
sequence in number of multi-frames. Its value is equal to the number of
|
|
multi-frames minus one. In the current iteration of the peripheral, this
|
|
register is read-only and the ILAS will always last for four multi-frames. The
|
|
``LINK_CONFIG3`` register is used only in 8B/10B links and completely
|
|
disregarded in 64B/66B mode.
|
|
|
|
ILAS Configuration Data
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
For 8B/10B link layer the ILAS configuration data registers contain the
|
|
configuration data that is sent during the ILAS phase. Similar to the link
|
|
configuration registers, the ILAS configuration data registers can only be
|
|
modified while the link is disabled and turn read-only as soon as it is enabled.
|
|
|
|
For each lane there is a set of four registers (``LANEn_ILAS0``,
|
|
``LANEn_ILAS1``, ``LANEn_ILAS2``, ``LANEn_ILAS3``) that allow access to the 14
|
|
configuration data octets. Aside from the ``LID`` and ``FCHK`` fields all fields
|
|
for each of the lanes map to the same internal storage. This means only the
|
|
``LID`` and ``FCHK`` fields can be configured with per-lane configuration data,
|
|
all other fields must be set to the same value for all lanes.
|
|
|
|
SYSREF Handling
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
The external SYSREF signal is used to align the internal local multiframe clocks
|
|
(LMFC)/ local-multiblock-clock (LEMC) between multiple devices on the same link.
|
|
|
|
The ``SYSREF_CONF`` (``0x100``) register controls the behavior of the SYSREF
|
|
capture circuitry. Setting the ``SYSREF_DISABLE`` (``[0]``) bit to 1 disables
|
|
the SYSREF handling. All external SYSREF events are ignored and the LMFC/LEMC is
|
|
generated internally. For Subclass 1 operation SYSREF handling should be enabled
|
|
and for Subclass 0 operation it should be disabled.
|
|
|
|
The ``SYSREF_LMFC_OFFSET`` (``0x104``) register allows modifying the offset
|
|
between the SYSREF rising edge and the rising edge of the LMFC/LEMC. Must be a
|
|
multiple of ``DATA_PATH_WIDTH``.
|
|
|
|
For optimal operation, it is recommended that all device on a JESD204 link
|
|
should be configured in a way so that the total offset between
|
|
|
|
The value of the ``SYSREF_LMFC_OFFSET`` register must be set to a value smaller
|
|
than the configured number of octets-per-multiframe (``OCTETS_PER_MULTIFRAME``),
|
|
otherwise undefined behavior might occur.
|
|
|
|
The ``SYSREF_STATUS`` (``0x108``) register allows monitoring the status of the
|
|
SYSREF signals. ``SYSREF_DETECTED`` (``[0]``) bit indicates that the peripheral
|
|
as observed a SYSREF event. The ``SYSREF_ALIGNMENT_ERROR`` (``[1]``) bit
|
|
indicates that a SYSREF event has been observed which was unaligned, in regards
|
|
to the LMFC period, to a previously recorded SYSREF event.
|
|
|
|
All bits in the ``SYSREF_STATUS`` register are write-to-clear. All bits will
|
|
also be cleared when the link is disabled.
|
|
|
|
Note that the ``SYSREF_STATUS`` register will not record any events if SYSREF
|
|
operation is disabled or the JESD204 link is disabled.
|
|
|
|
Link Status
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
All link status registers are read-only. While the link is disabled some of the
|
|
link status registers might contain bogus values. Their content should be
|
|
ignored until the link is fully enabled.
|
|
|
|
The ``STATUS_STATE`` (``[1:0]``) field of the ``LINK_STATUS`` (``0x280``)
|
|
register indicates the state of the
|
|
:ref:`8B/10B link state machine <axi_jesd204_tx_8b_10b_link_state_machine>`
|
|
or 64B/66B link state machine depending on the selected encoder. Possible
|
|
values are:
|
|
|
|
Possible values for a 8B/10B link are:
|
|
|
|
- 0: WAIT phase;
|
|
- 1: CGS phase;
|
|
- 2: ILAS phase;
|
|
- 3: DATA phase.
|
|
|
|
Possible values for a 64B/66B link are:
|
|
|
|
- 0: WAIT phase;
|
|
- 3: DATA phase.
|
|
|
|
The ``STATUS_SYNC`` (``[4]``) field represents the raw state of the external
|
|
SYNC~ and can be used to monitor whether the JESD204B converter device has
|
|
requested link synchronization. This is available only for 8B/10B links.
|
|
|
|
Manual Synchronization Request
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
For 8B/10B links the ``MANUAL_SYNC_REQUEST`` (``0x248``) register can be used to
|
|
transition the link state from the WAIT phase to the CGS phase in the absence of
|
|
an external synchronization request. This is useful for test cases where the
|
|
peripheral is connected to signal analyzer instead of a JESD204B receiver
|
|
device.
|
|
|
|
Writing a 1 to this register will trigger a manual synchronization request.
|
|
Writing the register while the link is disabled or writing a 0 to the register
|
|
has no effect. The register is self-clearing and reading it will always return
|
|
0.
|
|
|
|
This feature is useful if the ``SYNC~`` is stuck high from some reason. Setting
|
|
the ``MANUAL_SYNC_REQUEST`` bit will bring out the Tx link peripheral from
|
|
``CGS`` and will continue with sending ``ILAS`` and ``DATA`` information. After
|
|
this, the ``SYNC_STATUS`` bit would read high, and ``LINK_STATE`` would be
|
|
``DATA``.
|
|
|
|
If the ``SYNC~`` is stuck low, writing the ``MANUAL_SYNC_REQUEST`` would not do
|
|
too much, the link would stay in ``CGS`` and wait the de-assertion of ``SYNC~``
|
|
which won't happen. In this case the ``SYNC_STATUS`` would stay low and
|
|
``LINK_STATE``\ would be ``CGS``.
|
|
|
|
Clock Monitor
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
The ``LINK_CLK_FREQ`` (``0x0c8``) register allows to determine the clock rate of
|
|
the link clock (``clk``) relative to the AXI interface clock (``s_axi_aclk``).
|
|
This can be used to verify that the link clock is running at the expected rate.
|
|
|
|
The ``DEVICE_CLK_FREQ`` (``0x0cc``) register allows to determine the clock rate
|
|
of the device clock (``device_clk``) relative to the AXI interface clock
|
|
(``s_axi_aclk``). This can be used to verify that the device clock is running at
|
|
the expected rate.
|
|
|
|
The number is represented as unsigned 16.16 format. Assuming a 100MHz processor
|
|
clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0
|
|
indicates that the link clock is currently not active.
|
|
|
|
.. _axi_jesd204_tx_interrupts:
|
|
|
|
Interrupts
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
The core does not generate interrupts.
|
|
|
|
8B/10B Link
|
|
--------------------------------------------------------------------------------
|
|
|
|
.. image:: axi_jesd204_tx_204c_8b10b.svg
|
|
:align: center
|
|
|
|
.. _axi_jesd204_tx_8b_10b_link_state_machine:
|
|
|
|
8B/10B Link State Machine
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
.. image:: jesd204_tx_state_machine.svg
|
|
:align: right
|
|
|
|
The peripheral can be in one of four main operating phases: WAIT, CGS, ILAS or
|
|
DATA. Upon reset the peripheral starts in the WAIT phase. The CGS and ILAS
|
|
phases are used during the initialization of the JESD204B link. The DATA phase
|
|
is used during normal operation when user data is transmitted across the
|
|
JESD204B link.
|
|
|
|
Wait Phase (WAIT)
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
The WAIT phase is the default state entered during reset. While disabled the
|
|
peripheral will stay in the WAIT phase. When enabled, the peripheral will stay
|
|
in the WAIT phase until a synchronization request is received.
|
|
|
|
A synchronization request can either be generated manually through the register
|
|
map configuration interface or by one of the JESD204B receivers by asserting the
|
|
``SYNC~`` signal. Once a synchronization request is received the peripheral
|
|
transitions to the CGS phase.
|
|
|
|
During the WAIT phase the peripheral will continuously transmit
|
|
:dokuwiki:`/K/ control character <resources/fpga/peripherals/jesd204/jesd204_glossary#control_characters>`
|
|
on each of the ``TX_PHYn`` interfaces.
|
|
|
|
If at any point the peripheral is disabled, it will automatically transition
|
|
back to the WAIT state.
|
|
|
|
Lanes that have been disabled in the register map configuration interface, will
|
|
behave as if the link was in the WAIT state regardless of the actual state.
|
|
|
|
Code Group Synchronization Phase (CGS)
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
During the CGS phase the peripheral will continuously transmit
|
|
:dokuwiki:`/K/ control character <resources/fpga/peripherals/jesd204/jesd204_glossary#control_characters>`
|
|
on each of the ``TX_PHYn`` interfaces.
|
|
|
|
The peripheral will stay in the CGS phase until all of following conditions are
|
|
satisfied:
|
|
|
|
- The synchronization request is de-asserted;
|
|
- The CGS phase has lasted for at least the configured minimum CGS duration (1
|
|
frame + 9 octets by default);
|
|
- The end of a multi-frame is reached (This means the next phase will start at
|
|
the beginning of a multi-frame);
|
|
- The SYSREF signal has been captured and the LMFC is properly aligned.
|
|
|
|
If the peripheral is configured for continuous CGS operation it will stay in the
|
|
CGS phase indefinitely regardless of whether the above conditions are met or
|
|
not.
|
|
|
|
By default the peripheral will transition to the ILAS phase at the end of the
|
|
CGS phase. If the core is configured to skip the ILAS phase it will instead
|
|
directly transition to the DATA phase.
|
|
|
|
Initial Lane Alignment Sequence Phase (ILAS)
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
During the ILAS phase the peripheral transmits the initial lane alignment
|
|
sequence. The transmitted ILAS consists of four multi-frames. The first octet of
|
|
each multi-frame is the
|
|
:dokuwiki:`/R/ control character <resources/fpga/peripherals/jesd204/jesd204_glossary#control_characters>`
|
|
and the last octet of each multi-frame is the
|
|
:dokuwiki:`/A/ control character <resources/fpga/peripherals/jesd204/jesd204_glossary#control_characters>`.
|
|
|
|
During the second multi-frame the link configuration data is transmitted from
|
|
the 3rd to 16th octet. The second octet of the second multi-frame is the
|
|
:dokuwiki:`/Q/ control character <resources/fpga/peripherals/jesd204/jesd204_glossary#control_characters>`
|
|
to indicate that this multi-frame carries configuration data. The ILAS
|
|
configuration data sequence can be programmed through the register map
|
|
configuration interface.
|
|
|
|
All other octets of the ILAS sequence will contain the numerical value
|
|
corresponding to the position of the octet in the ILAS sequence (E.g. the fifth
|
|
octet of the first multi-frame contains the value 4).
|
|
|
|
.. wavedrom::
|
|
|
|
{
|
|
signal:
|
|
[
|
|
{ name: "ILAS", wave: "x35x|.54378x|x5435x|.5435x|x54", data: ["/R/",
|
|
"D", "D", "/A/", "/R/", "/Q/", "C", "D", "/A/", "/R/", "D", "D",
|
|
"/A/", "/R/", "D", "D", "A"] },
|
|
{ name: "LMFC", wave: 'pH..|l..H...|l..H..|l..H..|l..' },
|
|
],
|
|
config: { skin: 'narrow' }
|
|
}
|
|
|
|
By default the ILAS is transmitted for a duration of 4 multi-frames. After the
|
|
last ILAS multi-frame the peripheral switches to the DATA phase.
|
|
|
|
If the peripheral is configured for continuous ILAS operation it will instead
|
|
remain in the ILAS phase indefinitely. In continuous ILAS mode the peripheral
|
|
will transition back to the first multi-frame of the ILAS sequence after the
|
|
last multi-frame has been transmitted.
|
|
|
|
In accordance with the JESD204B standard the data transmitted during the ILAS
|
|
phase is not scrambled regardless of whether scrambling is enabled or not.
|
|
|
|
.. _axi_jesd204_tx_user_data_phase:
|
|
|
|
User Data Phase (DATA)
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
The DATA phase is the main operating mode of the peripheral. In this phase it
|
|
will receive transport layer data at the ``TX_DATA`` port, split it onto the
|
|
corresponding lanes and perform per-lane processing of the data according to the
|
|
peripherals configuration. When the peripheral enters the DATA phase the
|
|
``ready`` signal of the ``TX_DATA`` will be asserted to indicate that transport
|
|
layer data is now accepted.
|
|
|
|
By default the data transmitted on each lane will be scrambled. Scrambling can
|
|
optionally be disabled via the register map configuration interface. Scrambling
|
|
is enabled or disabled for all lanes equally.
|
|
|
|
Scrambling reduces data-dependent effects, which can affect both the analog
|
|
performance of the data converter as well as the bit-error rate of JESD204B
|
|
serial link, therefore it is highly recommended to enable scrambling.
|
|
|
|
The peripheral also performs per-lane alignment character replacement. Alignment
|
|
character replacement will replace under certain predictable conditions (i.e.
|
|
the receiver can recover the replaced character) the last octet in a frame or
|
|
multi-frame. Replaced characters at the end of a frame, that is also the end of
|
|
a multi-frame, are replaced by the
|
|
:dokuwiki:`/A/ character <resources/fpga/peripherals/jesd204/jesd204_glossary#control_characters>`.
|
|
Replaced characters at the end of a frame, that is not the end of a
|
|
multi-frame, are replaced by the
|
|
:dokuwiki:`/F/ character <resources/fpga/peripherals/jesd204/jesd204_glossary#control_characters>`.
|
|
Alignment characters can be used by the receiver to ensure proper frame
|
|
and lane alignment.
|
|
|
|
Alignment character replacement can optionally be disabled via the register map
|
|
configuration interface. Alignment character replacement is enabled or disabled
|
|
for all lanes equally. Alignment character replacement is only available when
|
|
scrambling is enabled and must be disabled when scrambling is disabled,
|
|
otherwise undefined behavior might occur.
|
|
|
|
Data on the ``TX_DATA`` port corresponding to a disabled lane is ignored.
|
|
|
|
8B/10B Multi-endpoint TX link establishment
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
In a multi-endpoint configuration one link transmit peripheral connects to
|
|
several endpoints/converter devices. In such cases the link is established
|
|
only when all enabled endpoints reach the DATA phase. For that all endpoints
|
|
must pass through CGS and ILAS stages. Depending on the software
|
|
implementation that controls the converter devices the endpoints can be
|
|
enabled at different moments. The link transmit peripheral will send CGS
|
|
characters until all enabled endpoints succeeded character alignment and
|
|
signalize that through the de-assertion of ``SYNC~`` signal.
|
|
In the below example we have a multi-point link of four endpoints
|
|
(``NUM_LINKS`` = 4):
|
|
|
|
.. image:: quadmxfe_linkbringup_204b_dac.svg
|
|
:align: center
|
|
|
|
.. note::
|
|
|
|
The physical layer is not depicted on purpose. JRXn represents the link
|
|
layer counterpart in the converter device/endpoint *n*.
|
|
|
|
The steps of the link bring-up are presented below:
|
|
|
|
- **1** - Link transmit peripheral is enabled, will start to send ``CGS``
|
|
characters on all lanes regardless of the state of the ``SYNC~`` signal;
|
|
- **2,3,4,5** - JESD Receive block of ADC enabled, its corresponding ``SYNC~``
|
|
pin is pulled low. The timing depends on the software implementation that
|
|
controls the ADC;
|
|
- **6** - In Subclass 1 (SC1) ``SYSREF`` is captured and ``LMFC`` in the
|
|
FPGA and converter device is adjusted;
|
|
- **7** - Once the ``CGS`` characters are received correctly, on the next
|
|
Frame clock boundary in SC0 or ``LMFC`` boundary in SC1 the ``SYNC~`` is
|
|
de-asserted;
|
|
- **8** - Once all enabled endpoints (not masked by ``MULTI_LINK_DISABLE``)
|
|
de-assert the ``SYNC~`` signal, on the next Frame clock boundary for SC0 or
|
|
the next ``LMFC`` boundary for SC1, the transmit peripheral will start
|
|
sending the ``ILAS`` sequence, then ``MFRAMES_PER_ILAS`` (typically 4)
|
|
``LMFC`` periods later the actual ``DATA``. **In SC1 if** ``SYSREF`` **is not
|
|
captured the link transmit peripheral will stay in CGS state.**
|
|
|
|
Diagnostics
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
:dokuwiki:`Troubleshooting JESD204B Tx links <resources/fpga/peripherals/jesd204/jesd204_troubleshooting>`
|
|
|
|
64B/66B Link
|
|
--------------------------------------------------------------------------------
|
|
|
|
.. image:: axi_jesd204_tx_204c_64b66b.svg
|
|
:align: center
|
|
|
|
The 64-bit wide datapath of the link layer is fairly simple, the only mandatory
|
|
part of the 64B66B link layer datapath is the scrambler. This must be active
|
|
during the operation of the link, however for debug purposes can be bypasses
|
|
with a control register ``SCRAMBLER_DISABLE``.
|
|
|
|
The data is accepted from the upstream transport layer core once the local
|
|
extended multiblock clock (LEMC) is adjusted to the captured SYSREF signal. Once
|
|
this happened the data will be accepted without interruption until the link is
|
|
disabled since there is no back-pressure from the physical layer.
|
|
|
|
If the core does not receives at least one SYSREF pulse it will not pass any
|
|
data from transport layer to physical layer.
|
|
|
|
For each multiblock sent on the data interface a CRC is calculated which is sent
|
|
on the 2-bit sync header stream during the next multiblock period. Beside the
|
|
CRC the sync header stream contains synchronization information to mark the
|
|
boundary of the multiblock and extended multiblocks.
|
|
|
|
Dual clock operation
|
|
--------------------------------------------------------------------------------
|
|
|
|
In case ``ASYNC_CLK`` parameter is set, a gearbox with 4:N (204B) or 8:N (204C)
|
|
ratio is enabled in the link layer peripherals, where N depends on the F
|
|
parameter of the link. The goal of the gearbox is to have at the transport
|
|
layer interface a data width that contains an integer number of frames per
|
|
every device clock cycle (each beat) so an integer number of samples can be
|
|
delivered/consumed to/from the application layer aligned to SYSREF ensuring
|
|
deterministic latency in modes where N'=12 or F!=1,2,4.
|
|
|
|
.. image:: dual_clock_operation.svg
|
|
:align: center
|
|
|
|
The gearbox ratio corresponds with the ratio of the link layer interface data
|
|
width towards physical layer and transport layer in octets. The interface width
|
|
towards the physical layer in 8B/10B (204B) mode depends on the DATA_PATH_WIDTH
|
|
synthesis parameter, and can be either 4 octets (default) or 8 octets. In 204B
|
|
mode the util_adxcvr supports only data width of 4 octets. In 64b66b (aka 204C)
|
|
mode the data width towards the physical interface is always 8 octets.
|
|
|
|
The data path width towards the transport layer is defined by the
|
|
TPL_DATA_PATH_WIDTH synthesis parameter.
|
|
|
|
The following rules apply:
|
|
|
|
- TPL_DATA_PATH_WIDTH >= DATA_PATH_WIDTH;
|
|
- TPL_DATA_PATH_WIDTH = m x F; where m is a positive integer, power of 2.
|
|
|
|
The link clock and device clock ratio should be the inverse of the
|
|
DATA_PATH_WIDTH : TPL_DATA_PATH_WIDTH ratio.
|
|
|
|
In this context the link clock will be lane rate/40 or lane rate/80 for 204B
|
|
depending on DATA_PATH_WIDTH and lane rate / 66 for 204C 64B/66B, however the
|
|
device clock could vary based in the F parameter.
|
|
|
|
Software Support
|
|
--------------------------------------------------------------------------------
|
|
|
|
.. warning::
|
|
|
|
To ensure correct operation it is highly recommended to use the
|
|
Analog Devices provided JESD204B software packages for interfacing the
|
|
peripheral. Analog Devices is not able to provide support in case issues arise
|
|
from using custom low-level software for interfacing the peripheral.
|
|
|
|
- :dokuwiki:`JESD204B Transmit Linux Driver Support <resources/tools-software/linux-drivers/jesd204/axi_jesd204_tx>`
|
|
|
|
Restrictions
|
|
--------------------------------------------------------------------------------
|
|
|
|
During the design of the peripheral the deliberate decision was made to support
|
|
only a subset of the features mandated by the JESD204B standard for transmitter
|
|
logic devices. The reasoning here is that the peripheral has been designed to
|
|
interface to Analog Devices JESD204B DAC converter devices and features that are
|
|
either not required or not supported by those converter devices would otherwise
|
|
lie dormant in peripheral and never be used. Instead the decision was made to
|
|
not implement those unneeded features even when the JESD204B standard requires
|
|
them for general purpose JESD204B transmitter logic devices. As Analog Devices
|
|
DAC converter devices with new requirements are released the peripheral will be
|
|
adjusted accordingly.
|
|
|
|
This approach allows for a leaner design using less resources, allowing for
|
|
lower pipeline latency and a higher maximum device clock frequency.
|
|
|
|
The following lists where the peripheral deviates from the standard:
|
|
|
|
- No subclass 2 support. JESD204B subclass 2 has due to its implementation
|
|
details restricted applicability and is seldom a viable option for a modern
|
|
high-speed data converter system. To achieve deterministic latency it is
|
|
recommend to use subclass 1 mode;
|
|
- Reduced number of octets-per-frame settings. The JESD204B standard allows for
|
|
any value between 1 and 256 to be used for the number of octets-per-frame;
|
|
- The following octets-per-frame values are supported by the peripheral: 1, 2,
|
|
4 and 8.(No longer applies starting from 1.06.a);
|
|
- Reduced number of frames-per-multi-frame settings. The following values are
|
|
supported by the peripheral: 1-32, with the additional requirement that F*K
|
|
is a multiple of 4. In addition F*K needs to be in the range of 4-256;
|
|
- No support for alignment character replacement when scrambling is
|
|
disabled.(No longer applies starting from 1.06.a).
|
|
|
|
.. _axi_jesd204_tx_supported_devices:
|
|
|
|
Supported Devices
|
|
--------------------------------------------------------------------------------
|
|
|
|
JESD204B Digital-to-Analog Converters
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- :adi:`AD9135 <en/products/AD9135>`: Dual, 11-Bit, high dynamic, 2.8 GSPS,
|
|
TxDAC+® Digital-to-Analog Converter
|
|
- :adi:`AD9136 <en/products/AD9136>`: Dual, 16-Bit, 2.8 GSPS, TxDAC+®
|
|
Digital-to-Analog Converter
|
|
- :adi:`AD9144 <en/products/AD9144>`: Quad, 16-Bit, 2.8 GSPS, TxDAC+®
|
|
Digital-to-Analog Converter
|
|
- :adi:`AD9152 <en/products/AD9152>`: Dual, 16-Bit, 2.25 GSPS, TxDAC+
|
|
Digital-to-Analog Converter
|
|
- :adi:`AD9154 <en/products/AD9154>`: Quad, 16-Bit, 2.4 GSPS, TxDAC+®
|
|
Digital-to-Analog Converter
|
|
- :adi:`AD9161 <en/products/AD9161>`: 11-Bit, 12 GSPS, RF Digital-to-Analog
|
|
Converter
|
|
- :adi:`AD9162 <en/products/AD9162>`: 16-Bit, 12 GSPS, RF Digital-to-Analog
|
|
Converter
|
|
- :adi:`AD9163 <en/products/AD9163>`: 16-Bit, 12 GSPS, RF DAC and Digital
|
|
Upconverter
|
|
- :adi:`AD9164 <AD9164>`: 16-Bit, 12 GSPS, RF DAC and Direct Digital
|
|
Synthesizer
|
|
- :adi:`AD9172 <en/products/AD9172>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
|
Channelizers
|
|
- :adi:`AD9173 <en/products/AD9173>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
|
Channelizers
|
|
- :adi:`AD9174 <en/products/AD9174>`: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct
|
|
Digital Synthesizer
|
|
- :adi:`AD9175 <en/products/AD9175>`: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with
|
|
Wideband Channelizers
|
|
- :adi:`AD9176 <en/products/AD9176>`: Dual, 16-Bit, 12.6 GSPS RF DAC with
|
|
Wideband Channelizers
|
|
- :adi:`AD9177 <en/products/AD9177>`: Quad, 16-Bit, 12 GSPS RF DAC with
|
|
Wideband Channelizers
|
|
|
|
JESD204B RF Transceivers
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- :adi:`AD9371 <en/products/AD9371>`: SDR Integrated, Dual RF Transceiver with
|
|
Observation Path
|
|
- :adi:`AD9375 <en/products/AD9375>`: SDR Integrated, Dual RF Transceiver with
|
|
Observation Path and DPD
|
|
- :adi:`ADRV9009 <en/products/ADRV9009>`: SDR Integrated, Dual RF Transceiver
|
|
with Observation Path
|
|
- :adi:`ADRV9008-1 <en/products/ADRV9008-1>`: SDR Integrated, Dual RF Receiver
|
|
- :adi:`ADRV9008-2 <en/products/ADRV9008-2>`: SDR Integrated, Dual RF
|
|
Transmitter with Observation Path
|
|
|
|
JESD204B/C Mixed-Signal Front Ends
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- :adi:`AD9081 <en/products/AD9081>`: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and
|
|
Quad, 12-Bit, 4GSPS RFADC
|
|
- :adi:`AD9082 <en/products/AD9082>`: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and
|
|
DUAL, 12-Bit, 6GSPS RFADC
|
|
- :adi:`AD9986 <en/products/AD9986>`: 4T2R Direct RF Transmitter and
|
|
Observation Receiver
|
|
- :adi:`AD9988 <en/products/AD9988>`: 4T4R Direct RF Receiver and Transmitter
|
|
|
|
Technical Support
|
|
--------------------------------------------------------------------------------
|
|
|
|
Analog Devices will provide limited online support for anyone using the core
|
|
with Analog Devices components (ADC, DAC, Clock, etc) via the
|
|
:ez:`EngineerZone <fpga>` under the GPL license. If you would like
|
|
deterministic support when using this core with an ADI component, please
|
|
investigate a commercial license. Using a non-ADI JESD204 device with this core
|
|
is possible under the GPL, but Analog Devices will not help with issues you may
|
|
encounter.
|
|
|
|
More Information
|
|
--------------------------------------------------------------------------------
|
|
|
|
- :ref:`JESD204B High-Speed Serial Interface Support <jesd204>`
|
|
- :ref:`HDL User Guide <user_guide>`
|