473 lines
17 KiB
Systemverilog
473 lines
17 KiB
Systemverilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_pwm_gen #(
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parameter ID = 0,
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parameter ASYNC_CLK_EN = 1,
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parameter N_PWMS = 1,
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parameter PWM_EXT_SYNC = 0,
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parameter EXT_ASYNC_SYNC = 0,
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parameter SOFTWARE_BRINGUP = 1,
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parameter EXT_SYNC_PHASE_ALIGN = 0,
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parameter FORCE_ALIGN = 0,
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parameter START_AT_SYNC = 1,
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parameter PULSE_0_WIDTH = 7,
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parameter PULSE_1_WIDTH = 7,
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parameter PULSE_2_WIDTH = 7,
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parameter PULSE_3_WIDTH = 7,
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parameter PULSE_4_WIDTH = 7,
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parameter PULSE_5_WIDTH = 7,
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parameter PULSE_6_WIDTH = 7,
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parameter PULSE_7_WIDTH = 7,
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parameter PULSE_8_WIDTH = 7,
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parameter PULSE_9_WIDTH = 7,
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parameter PULSE_10_WIDTH = 7,
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parameter PULSE_11_WIDTH = 7,
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parameter PULSE_12_WIDTH = 7,
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parameter PULSE_13_WIDTH = 7,
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parameter PULSE_14_WIDTH = 7,
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parameter PULSE_15_WIDTH = 7,
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parameter PULSE_0_PERIOD = 10,
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parameter PULSE_1_PERIOD = 10,
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parameter PULSE_2_PERIOD = 10,
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parameter PULSE_3_PERIOD = 10,
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parameter PULSE_4_PERIOD = 10,
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parameter PULSE_5_PERIOD = 10,
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parameter PULSE_6_PERIOD = 10,
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parameter PULSE_7_PERIOD = 10,
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parameter PULSE_8_PERIOD = 10,
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parameter PULSE_9_PERIOD = 10,
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parameter PULSE_10_PERIOD = 10,
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parameter PULSE_11_PERIOD = 10,
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parameter PULSE_12_PERIOD = 10,
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parameter PULSE_13_PERIOD = 10,
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parameter PULSE_14_PERIOD = 10,
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parameter PULSE_15_PERIOD = 10,
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parameter PULSE_0_OFFSET = 0,
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parameter PULSE_1_OFFSET = 0,
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parameter PULSE_2_OFFSET = 0,
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parameter PULSE_3_OFFSET = 0,
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parameter PULSE_4_OFFSET = 0,
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parameter PULSE_5_OFFSET = 0,
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parameter PULSE_6_OFFSET = 0,
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parameter PULSE_7_OFFSET = 0,
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parameter PULSE_8_OFFSET = 0,
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parameter PULSE_9_OFFSET = 0,
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parameter PULSE_10_OFFSET = 0,
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parameter PULSE_11_OFFSET = 0,
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parameter PULSE_12_OFFSET = 0,
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parameter PULSE_13_OFFSET = 0,
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parameter PULSE_14_OFFSET = 0,
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parameter PULSE_15_OFFSET = 0
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) (
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input ext_clk,
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input ext_sync,
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output pwm_0,
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output pwm_1,
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output pwm_2,
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output pwm_3,
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output pwm_4,
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output pwm_5,
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output pwm_6,
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output pwm_7,
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output pwm_8,
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output pwm_9,
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output pwm_10,
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output pwm_11,
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output pwm_12,
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output pwm_13,
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output pwm_14,
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output pwm_15
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);
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// local parameters
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localparam PWMS = N_PWMS-1;
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localparam [31:0] CORE_VERSION = {16'h0002, /* MAJOR */
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8'h01, /* MINOR */
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8'h01}; /* PATCH */
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localparam [31:0] CORE_MAGIC = 32'h601a3471; // PLSG
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localparam reg [31:0] PULSE_WIDTH_G[15:0] = '{PULSE_0_WIDTH,
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PULSE_1_WIDTH,
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PULSE_2_WIDTH,
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PULSE_3_WIDTH,
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PULSE_4_WIDTH,
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PULSE_5_WIDTH,
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PULSE_6_WIDTH,
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PULSE_7_WIDTH,
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PULSE_8_WIDTH,
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PULSE_9_WIDTH,
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PULSE_10_WIDTH,
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PULSE_11_WIDTH,
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PULSE_12_WIDTH,
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PULSE_13_WIDTH,
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PULSE_14_WIDTH,
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PULSE_15_WIDTH};
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localparam reg [31:0] PULSE_PERIOD_G[0:15] = '{PULSE_0_PERIOD,
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PULSE_1_PERIOD,
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PULSE_2_PERIOD,
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PULSE_3_PERIOD,
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PULSE_4_PERIOD,
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PULSE_5_PERIOD,
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PULSE_6_PERIOD,
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PULSE_7_PERIOD,
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PULSE_8_PERIOD,
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PULSE_9_PERIOD,
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PULSE_10_PERIOD,
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PULSE_11_PERIOD,
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PULSE_12_PERIOD,
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PULSE_13_PERIOD,
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PULSE_14_PERIOD,
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PULSE_15_PERIOD};
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localparam reg [31:0] PULSE_OFFSET_G[0:15] = '{PULSE_0_OFFSET,
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PULSE_1_OFFSET,
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PULSE_2_OFFSET,
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PULSE_3_OFFSET,
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PULSE_4_OFFSET,
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PULSE_5_OFFSET,
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PULSE_6_OFFSET,
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PULSE_7_OFFSET,
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PULSE_8_OFFSET,
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PULSE_9_OFFSET,
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PULSE_10_OFFSET,
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PULSE_11_OFFSET,
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PULSE_12_OFFSET,
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PULSE_13_OFFSET,
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PULSE_14_OFFSET,
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PULSE_15_OFFSET};
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// internal registers
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reg [PWMS:0] sync;
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reg [31:0] offset_cnt = 32'd0;
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reg offset_alignment = 1'b1;
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reg [31:0] pwm_offset_d[0:PWMS];
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reg [31:0] pwm_offset_read[0:PWMS];
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// internal signals
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wire clk;
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wire up_clk;
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wire up_rstn;
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wire up_rreq_s;
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wire up_wack_s;
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wire up_rack_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire [ 15:0] pwm;
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wire [ 31:0] pwm_width_s[0:PWMS];
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wire [ 31:0] pwm_period_s[0:PWMS];
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wire [ 31:0] pwm_offset_s[0:PWMS];
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wire [ 15:0] pwm_armed;
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wire load_config_s;
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wire start_at_sync_s;
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wire force_align_s;
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wire ext_sync_align_s;
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wire [ 15:0] ready_to_align_s;
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wire [ 15:0] active_channel_s;
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wire pwm_gen_resetn;
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wire ext_sync_s;
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wire new_alignment;
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wire pause_cnt;
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wire enable_wait;
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wire wait_for_all;
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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axi_pwm_gen_regmap #(
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.ID (ID),
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.ASYNC_CLK_EN (ASYNC_CLK_EN),
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.SOFTWARE_BRINGUP (SOFTWARE_BRINGUP),
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.EXT_SYNC_PHASE_ALIGN (EXT_SYNC_PHASE_ALIGN),
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.FORCE_ALIGN (FORCE_ALIGN),
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.START_AT_SYNC (START_AT_SYNC),
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.CORE_MAGIC (CORE_MAGIC),
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.CORE_VERSION (CORE_VERSION),
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.N_PWMS (PWMS),
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.PULSE_WIDTH_G (PULSE_WIDTH_G),
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.PULSE_PERIOD_G (PULSE_PERIOD_G),
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.PULSE_OFFSET_G (PULSE_OFFSET_G)
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) i_regmap (
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.ext_clk (ext_clk),
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.clk_out (clk),
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.pwm_gen_resetn (pwm_gen_resetn),
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.pwm_width (pwm_width_s),
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.pwm_period (pwm_period_s),
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.pwm_offset (pwm_offset_s),
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.load_config (load_config_s),
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.start_at_sync (start_at_sync_s),
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.force_align (force_align_s),
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.ext_sync_align (ext_sync_align_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// external sync
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generate
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reg ext_sync_m0 = 1'b1;
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reg ext_sync_m1 = 1'b1;
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if (EXT_ASYNC_SYNC) begin
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always @(posedge clk) begin
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if (pwm_gen_resetn == 1'b0) begin
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ext_sync_m0 <= 1'b1;
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ext_sync_m1 <= 1'b1;
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end else begin
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ext_sync_m0 <= (PWM_EXT_SYNC == 1) ? ext_sync : 0;
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ext_sync_m1 <= ext_sync_m0;
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end
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end
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assign ext_sync_s = ext_sync_m1;
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end else begin
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assign ext_sync_s = (PWM_EXT_SYNC == 1) ? ext_sync : 0;
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end
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endgenerate
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assign new_alignment = load_config_s | ext_sync_s & ext_sync_align_s;
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// offset counter
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always @(posedge clk) begin
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if (offset_alignment == 1'b1 || pwm_gen_resetn == 1'b0 || ext_sync_s == 1'b1) begin
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offset_cnt <= 32'd0;
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end else begin
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offset_cnt <= offset_cnt + 1'b1;
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end
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if (pwm_gen_resetn == 1'b0) begin
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offset_alignment <= 1'b1;
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end else begin
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// the offset alignment by external sync has two options
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// 1. event on a faster clock(2'nd async clk) cannot be sampled on the base
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// external clock.
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// 2. fall edge
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// when using external sync an offset alignment can only be done
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// after all pwm counters are paused(load_config)/reseated while the
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// external sync is held high
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offset_alignment <= (new_alignment == 1'b1) ? 1'b1 :
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offset_alignment &
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(ext_sync_s ? 1'b1 : pause_cnt);
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end
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end
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assign enable_wait = ((pwm_armed[0] & active_channel_s[0]) |
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(pwm_armed[1] & active_channel_s[1]) |
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(pwm_armed[2] & active_channel_s[2]) |
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(pwm_armed[3] & active_channel_s[3]) |
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(pwm_armed[4] & active_channel_s[4]) |
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(pwm_armed[5] & active_channel_s[5]) |
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(pwm_armed[6] & active_channel_s[6]) |
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(pwm_armed[7] & active_channel_s[7]) |
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(pwm_armed[8] & active_channel_s[8]) |
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(pwm_armed[9] & active_channel_s[9]) |
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(pwm_armed[10] & active_channel_s[10]) |
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(pwm_armed[11] & active_channel_s[11]) |
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(pwm_armed[12] & active_channel_s[12]) |
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(pwm_armed[13] & active_channel_s[13]) |
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(pwm_armed[14] & active_channel_s[14]) |
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(pwm_armed[15] & active_channel_s[15]));
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assign wait_for_all = (pwm_armed[0] &
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pwm_armed[1] &
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pwm_armed[2] &
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pwm_armed[3] &
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pwm_armed[4] &
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pwm_armed[5] &
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pwm_armed[6] &
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pwm_armed[7] &
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pwm_armed[8] &
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pwm_armed[9] &
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pwm_armed[10] &
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pwm_armed[11] &
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pwm_armed[12] &
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pwm_armed[13] &
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pwm_armed[14] &
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pwm_armed[15]);
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assign pause_cnt = !(enable_wait & wait_for_all);
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genvar i;
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generate
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for (i = 0; i <= 15; i = i + 1) begin: pwm_cnt
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if (i <= PWMS) begin
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// flop the desired offset
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always @(posedge clk) begin
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if (pwm_gen_resetn == 1'b0) begin
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pwm_offset_d[i] <= pwm_offset_s[i];
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pwm_offset_read[i] <= pwm_offset_s[i];
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end else begin
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// load the input period/width values
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if (load_config_s) begin
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pwm_offset_read[i] <= pwm_offset_s[i];
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if (force_align_s == 1) begin
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pwm_offset_d[i] <= pwm_offset_s[i];
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end
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end
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// update the current period/width at the end of the period
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if (ready_to_align_s[i]) begin
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pwm_offset_d[i] <= pwm_offset_read[i];
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end
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end
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end
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axi_pwm_gen_1 #(
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.PULSE_WIDTH (PULSE_WIDTH_G[i]),
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.PULSE_PERIOD (PULSE_PERIOD_G[i])
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) i_axi_pwm_gen_1 (
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.clk (clk),
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.rstn (pwm_gen_resetn),
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.pulse_width (pwm_width_s[i]),
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.pulse_period (pwm_period_s[i]),
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.load_config (load_config_s),
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.start_at_sync_en (start_at_sync_s),
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.force_align_en (force_align_s),
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.ext_sync_align_en (ext_sync_align_s),
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.ext_sync (ext_sync_s),
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.sync (sync[i]),
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.pulse (pwm[i]),
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.active_channel (active_channel_s[i]),
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.ready_to_align (ready_to_align_s[i]),
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.pulse_armed (pwm_armed[i]));
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always @(posedge clk) begin
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if (pwm_gen_resetn == 1'b0) begin
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sync[i] <= 1'b1;
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end else begin
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sync[i] <= (offset_cnt == pwm_offset_d[i]) ? offset_alignment : 1'b1;
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end
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end
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end else begin
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assign pwm[i] = 1'b0;
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assign pwm_armed[i] = 1'b1;
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assign active_channel_s[i] = 1'b0;
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assign ready_to_align_s[i] = 1'b1;
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end
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end
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endgenerate
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assign pwm_0 = pwm[0];
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assign pwm_1 = pwm[1];
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assign pwm_2 = pwm[2];
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assign pwm_3 = pwm[3];
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assign pwm_4 = pwm[4];
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assign pwm_5 = pwm[5];
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assign pwm_6 = pwm[6];
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assign pwm_7 = pwm[7];
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assign pwm_8 = pwm[8];
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assign pwm_9 = pwm[9];
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assign pwm_10 = pwm[10];
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assign pwm_11 = pwm[11];
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assign pwm_12 = pwm[12];
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assign pwm_13 = pwm[13];
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assign pwm_14 = pwm[14];
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assign pwm_15 = pwm[15];
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up_axi #(
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.AXI_ADDRESS_WIDTH(16)
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) i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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endmodule
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