c5d216bba9
For CMOS case, lane rates are so low that reference clock of the source synchronous interface can be routed on non-clock routes. The delays on the clock line are adjusted by the digital interface tuning controlled through software. Lock down clock buffers on Rx and Tx interfaces, this avoids suboptimal placement which causes large skew between clocks at the serdes pins. |
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| a10soc | ||
| common | ||
| zc706 | ||
| zcu102 | ||
| zed | ||
| Makefile | ||