581 lines
20 KiB
Tcl
581 lines
20 KiB
Tcl
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## Define the supported tool version
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set required_vivado_version "2021.1"
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if {[info exists ::env(REQUIRED_VIVADO_VERSION)]} {
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set required_vivado_version $::env(REQUIRED_VIVADO_VERSION)
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} elseif {[info exists REQUIRED_VIVADO_VERSION]} {
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set required_vivado_version $REQUIRED_VIVADO_VERSION
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}
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## Define the ADI_IGNORE_VERSION_CHECK environment variable to skip version check
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if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
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set IGNORE_VERSION_CHECK 1
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} elseif {![info exists IGNORE_VERSION_CHECK]} {
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set IGNORE_VERSION_CHECK 0
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}
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## Define the ADI_USE_OOC_SYNTHESIS environment variable to enable out of context
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# synthesis
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if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} {
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if {[string equal $::env(ADI_USE_OOC_SYNTHESIS) n]} {
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set ADI_USE_OOC_SYNTHESIS 0
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} else {
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set ADI_USE_OOC_SYNTHESIS 1
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}
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} elseif {![info exists ADI_USE_OOC_SYNTHESIS]} {
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set ADI_USE_OOC_SYNTHESIS 1
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}
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## Set number of parallel out of context jobs through environment variable
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if {![info exists ::env(ADI_MAX_OOC_JOBS)]} {
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set ADI_MAX_OOC_JOBS 4
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} else {
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set ADI_MAX_OOC_JOBS $::env(ADI_MAX_OOC_JOBS)
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}
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## Set to enable incremental compilation
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set ADI_USE_INCR_COMP 1
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## Set to enable power optimization
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set ADI_POWER_OPTIMIZATION 0
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## Initialize global variables
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set p_board "not-applicable"
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set p_device "none"
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set sys_zynq 1
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set p_prcfg_init ""
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set p_prcfg_list ""
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set p_prcfg_status ""
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## Creates a Xilinx project for a given board
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#
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# \param[project_name] - name of the project
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# \param[mode] - if set non-project mode will be used, otherwise project mode
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# flow, see UG892 for more information
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# \param[parameter_list] - a list of global parameters (parameters of the
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# system_top module)
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#
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# Supported carrier names are: ac701, kc705, vc707, vcu118, kcu105, zed,
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# microzed, zc702, zc706, mitx405, zcu102.
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#
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proc adi_project {project_name {mode 0} {parameter_list {}} } {
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set device ""
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set board ""
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# Determine the device based on the board name
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if [regexp "_ac701$" $project_name] {
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set device "xc7a200tfbg676-2"
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set board [lindex [lsearch -all -inline [get_board_parts] *ac701*] end]
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}
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if [regexp "_kc705$" $project_name] {
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set device "xc7k325tffg900-2"
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set board [lindex [lsearch -all -inline [get_board_parts] *kc705*] end]
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}
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if [regexp "_vc707$" $project_name] {
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set device "xc7vx485tffg1761-2"
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set board [lindex [lsearch -all -inline [get_board_parts] *vc707*] end]
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}
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if [regexp "_vcu118$" $project_name] {
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set device "xcvu9p-flga2104-2L-e"
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set board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end]
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}
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if [regexp "_kcu105$" $project_name] {
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set device "xcku040-ffva1156-2-e"
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set board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end]
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}
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if [regexp "_zed$" $project_name] {
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set device "xc7z020clg484-1"
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set board [lindex [lsearch -all -inline [get_board_parts] *zed*] end]
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}
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if [regexp "_coraz7s$" $project_name] {
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set device "xc7z007sclg400-1"
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set board "not-applicable"
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}
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if [regexp "_microzed$" $project_name] {
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set device "xc7z010clg400-1"
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set board "not-applicable"
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}
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if [regexp "_zc702$" $project_name] {
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set device "xc7z020clg484-1"
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set board [lindex [lsearch -all -inline [get_board_parts] *zc702*] end]
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}
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if [regexp "_zc706$" $project_name] {
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set device "xc7z045ffg900-2"
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set board [lindex [lsearch -all -inline [get_board_parts] *zc706*] end]
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}
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if [regexp "_mitx045$" $project_name] {
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set device "xc7z045ffg900-2"
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set board "not-applicable"
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}
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if [regexp "_zcu102$" $project_name] {
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set device "xczu9eg-ffvb1156-2-e"
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set board [lindex [lsearch -all -inline [get_board_parts] *zcu102*] end]
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}
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if [regexp "_vmk180_es1$" $project_name] {
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enable_beta_device xcvm*
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xhub::refresh_catalog [xhub::get_xstores xilinx_board_store]
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xhub::install [xhub::get_xitems xilinx.com:xilinx_board_store:vmk180_es:*] -quiet
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set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
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set device "xcvm1802-vsva2197-2MP-e-S-es1"
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set board [lindex [lsearch -all -inline [get_board_parts] *vmk180_es*] end]
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}
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if [regexp "_vmk180$" $project_name] {
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set device "xcvm1802-vsva2197-2MP-e-S"
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set board [lindex [lsearch -all -inline [get_board_parts] *vmk180*] end]
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}
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if [regexp "_vck190$" $project_name] {
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set device "xcvc1902-vsva2197-2MP-e-S"
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set board [lindex [lsearch -all -inline [get_board_parts] *vck190*] end]
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}
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adi_project_create $project_name $mode $parameter_list $device $board
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}
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## Creates a Xilinx project.
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#
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# \param[project_name] - name of the project
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# \param[mode] - if set non-project mode will be used, otherwise project mode
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# flow, see UG892 for more information
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# \param[parameter_list] - a list of global parameters (parameters of the
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# system_top module)
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# \param[device] - Canonical Xilinx device string
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# \param[board] - board BSP name (optional)
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#
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proc adi_project_create {project_name mode parameter_list device {board "not-applicable"}} {
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global ad_hdl_dir
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global ad_ghdl_dir
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global p_board
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global p_device
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global sys_zynq
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global required_vivado_version
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global IGNORE_VERSION_CHECK
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global ADI_USE_OOC_SYNTHESIS
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global ADI_USE_INCR_COMP
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## update the value of $p_device only if it was not already updated elsewhere
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if {$p_device eq "none"} {
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set p_device $device
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}
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set p_board $board
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if [regexp "^xc7z" $p_device] {
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set sys_zynq 1
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} elseif [regexp "^xczu" $p_device] {
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set sys_zynq 2
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} elseif [regexp "^xcv\[ecmph\]" $p_device] {
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set sys_zynq 3
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} else {
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set sys_zynq 0
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}
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set VIVADO_VERSION [version -short]
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if {$IGNORE_VERSION_CHECK} {
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if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} {
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puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
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puts -nonewline "expected $required_vivado_version, "
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puts -nonewline "got $VIVADO_VERSION.\n"
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}
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} else {
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if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} {
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puts -nonewline "ERROR: vivado version mismatch; "
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puts -nonewline "expected $required_vivado_version, "
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puts -nonewline "got $VIVADO_VERSION.\n"
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puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
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exit 2
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}
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}
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if {$mode == 0} {
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set project_system_dir "./$project_name.srcs/sources_1/bd/system"
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create_project $project_name . -part $p_device -force
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} else {
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set project_system_dir ".srcs/sources_1/bd/system"
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create_project -in_memory -part $p_device
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}
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if {$mode == 1} {
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file mkdir $project_name.data
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}
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if {$p_board ne "not-applicable"} {
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set_property board_part $p_board [current_project]
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}
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set lib_dirs $ad_hdl_dir/library
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if {$ad_hdl_dir ne $ad_ghdl_dir} {
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lappend lib_dirs $ad_ghdl_dir/library
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}
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# Set a common IP cache for all projects
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if {$ADI_USE_OOC_SYNTHESIS == 1} {
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if {[file exists $ad_hdl_dir/ipcache] == 0} {
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file mkdir $ad_hdl_dir/ipcache
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}
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config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache
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}
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set_property ip_repo_paths $lib_dirs [current_fileset]
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update_ip_catalog
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## Load custom message severity definitions
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if {![info exists ::env(ADI_DISABLE_MESSAGE_SUPPRESION)]} {
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source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
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}
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## In Vivado there is a limit for the number of warnings and errors which are
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## displayed by the tool for a particular error or warning; the default value
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## of this limit is 100.
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## Overrides the default limit to 2000.
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set_param messaging.defaultLimit 2000
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# Set parameters of the top level file
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# Make the same parameters available to system_bd.tcl
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set proj_params [get_property generic [current_fileset]]
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foreach {param value} $parameter_list {
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lappend proj_params $param=$value
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set ad_project_params($param) $value
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}
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set_property generic $proj_params [current_fileset]
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create_bd_design "system"
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source system_bd.tcl
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save_bd_design
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validate_bd_design
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if {$ADI_USE_OOC_SYNTHESIS == 1} {
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set_property synth_checkpoint_mode Hierarchical [get_files $project_system_dir/system.bd]
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} else {
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set_property synth_checkpoint_mode None [get_files $project_system_dir/system.bd]
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}
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generate_target {synthesis implementation} [get_files $project_system_dir/system.bd]
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if {$ADI_USE_OOC_SYNTHESIS == 1} {
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export_ip_user_files -of_objects [get_files $project_system_dir/system.bd] -no_script -sync -force -quiet
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create_ip_run [get_files $project_system_dir/system.bd]
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}
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make_wrapper -files [get_files $project_system_dir/system.bd] -top
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if {$mode == 0} {
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import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
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} else {
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write_hwdef -file "$project_name.data/$project_name.hwdef"
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}
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if {$ADI_USE_INCR_COMP == 1} {
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if {[file exists ./reference.dcp]} {
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set_property incremental_checkpoint ./reference.dcp [get_runs impl_1]
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}
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}
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}
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## Add source files to an exiting project.
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#
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# \param[project_name] - name of the project
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# \param[project_files] - list of project files
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#
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proc adi_project_files {project_name project_files} {
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foreach pfile $project_files {
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if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
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add_files -norecurse -fileset constrs_1 $pfile
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} else {
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add_files -norecurse -fileset sources_1 $pfile
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}
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}
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# NOTE: top file name is always system_top
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set_property top system_top [current_fileset]
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}
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## Run an existing project (generate bit stream).
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#
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# \param[project_name] - name of the project
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#
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proc adi_project_run {project_name} {
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global ADI_POWER_OPTIMIZATION
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global ADI_USE_OOC_SYNTHESIS
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global ADI_MAX_OOC_JOBS
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if {$ADI_USE_OOC_SYNTHESIS == 1} {
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launch_runs -jobs $ADI_MAX_OOC_JOBS system_*_synth_1 synth_1
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} else {
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launch_runs synth_1
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}
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wait_on_run synth_1
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open_run synth_1
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report_timing_summary -file timing_synth.log
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if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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}
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if {$ADI_POWER_OPTIMIZATION == 1} {
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set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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}
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set_param board.repoPaths [get_property LOCAL_ROOT_DIR [xhub::get_xstores xilinx_board_store]]
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launch_runs impl_1 -to_step write_bitstream
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wait_on_run impl_1
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open_run impl_1
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report_timing_summary -warn_on_violation -file timing_impl.log
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if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} {
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set csv_file resource_utilization.csv
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if {[ catch {
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xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet
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set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]]
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set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]]
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set worst_slack_setup [get_property SLACK [get_timing_paths -setup]]
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set worst_slack_hold [get_property SLACK [get_timing_paths -hold]]
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set fileRead [open $csv_file r]
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set lines [split [read $fileRead] "\n"]
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set names_line [lindex $lines end-3]
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set values_line [lindex $lines end-2]
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close $fileRead
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set fileWrite [open $csv_file w]
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puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack"
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puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold"
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close $fileWrite
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} issue ] != 0 } {
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puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed"
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}
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# Define a list of IPs for which to generate report utilization
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set IP_list {
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ad_ip_jesd_204_tpl_adc
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ad_ip_jesd_204_tpl_dac
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axi_jesd204_rx
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axi_jesd204_tx
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jesd204_rx
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jesd204_tx
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axi_adxcvr
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util_adxcvr
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axi_dmac
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util_cpack2
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util_upack2
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}
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foreach IP_name $IP_list {
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set output_file ${IP_name}_resource_utilization.log
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file delete $output_file
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foreach IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $IP_name || REF_NAME =~ $IP_name " ] {
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report_utilization -hierarchical -hierarchical_depth 1 -cells $IP_instance -file $output_file -append -quiet
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report_property $IP_instance -file $output_file -append -quiet
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set report_file [ open $output_file a ]
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puts $report_file "\n\n\n"
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close $report_file
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}
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}
|
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} else {
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puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set"
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}
|
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|
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if {[info exists ::env(ADI_GENERATE_XPA)]} {
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set csv_file power_analysis.csv
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set Layers "8to11"
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set CapLoad "20"
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set ToggleRate "15.00000"
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set StatProb "0.500000"
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|
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set_load $CapLoad [all_outputs]
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set_operating_conditions -board_layers $Layers
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set_switching_activity -default_toggle_rate $ToggleRate
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set_switching_activity -default_static_probability $StatProb
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set_switching_activity -type lut -toggle_rate $ToggleRate -static_probability $StatProb -all
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set_switching_activity -type register -toggle_rate $ToggleRate -static_probability $StatProb -all
|
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set_switching_activity -type shift_register -toggle_rate $ToggleRate -static_probability $StatProb -all
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set_switching_activity -type lut_ram -toggle_rate $ToggleRate -static_probability $StatProb -all
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set_switching_activity -type bram -toggle_rate $ToggleRate -static_probability $StatProb -all
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set_switching_activity -type dsp -toggle_rate $ToggleRate -static_probability $StatProb -all
|
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set_switching_activity -type gt_rxdata -toggle_rate $ToggleRate -static_probability $StatProb -all
|
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set_switching_activity -type gt_txdata -toggle_rate $ToggleRate -static_probability $StatProb -all
|
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set_switching_activity -type io_output -toggle_rate $ToggleRate -static_probability $StatProb -all
|
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set_switching_activity -type bram_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
|
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set_switching_activity -type bram_wr_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
|
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set_switching_activity -type io_bidir_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
|
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report_power -file $csv_file
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|
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set fileRead [open $csv_file r]
|
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set filecontent [read $fileRead]
|
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set input_list [split $filecontent "\n"]
|
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|
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set TextList [lsearch -all -inline $input_list "*Total On-Chip Power (W)*"]
|
|
set on_chip_pwr "[lindex [lindex $TextList 0] 6] W"
|
|
set TextList [lsearch -all -inline $input_list "*Junction Temperature (C)*"]
|
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set junction_temp "[lindex [lindex $TextList 0] 5] *C"
|
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close $fileRead
|
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|
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set fileWrite [open $csv_file w]
|
|
puts $fileWrite "On-chip_power,Junction_temp"
|
|
puts $fileWrite "$on_chip_pwr,$junction_temp"
|
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close $fileWrite
|
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} else {
|
|
puts "GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set"
|
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}
|
|
|
|
# Look for undefined clocks which do not show up in the timing summary
|
|
set timing_check [check_timing -override_defaults no_clock -no_header -return_string]
|
|
if {[regexp { (\d+) register} $timing_check -> num_regs]} {
|
|
|
|
if {[info exist num_regs]} {
|
|
if {$num_regs > 0} {
|
|
puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details."
|
|
check_timing -override_defaults no_clock -verbose -file no_clock.log
|
|
}
|
|
}
|
|
|
|
} else {
|
|
puts "CRITICAL WARNING: The search for undefined clocks failed !!!"
|
|
}
|
|
|
|
file mkdir $project_name.sdk
|
|
|
|
set timing_string $[report_timing_summary -return_string]
|
|
if { [string match "*VIOLATED*" $timing_string] == 1 ||
|
|
[string match "*Timing constraints are not met*" $timing_string] == 1} {
|
|
write_hw_platform -fixed -force -include_bit -file $project_name.sdk/system_top_bad_timing.xsa
|
|
return -code error [format "ERROR: Timing Constraints NOT met!"]
|
|
} else {
|
|
write_hw_platform -fixed -force -include_bit -file $project_name.sdk/system_top.xsa
|
|
}
|
|
}
|
|
|
|
## Run synthesis on an partial design; use it in Partial Reconfiguration flow.
|
|
#
|
|
# \param[project_name] - project name
|
|
# \param[prcfg_name] - name of the partial design
|
|
# \param[hdl_files] - hdl source of the partial design
|
|
# \param[xdc_files] - XDC constraint source of the partial design
|
|
#
|
|
proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
|
|
|
|
global p_device
|
|
|
|
set p_prefix "$project_name.data/$project_name"
|
|
|
|
if {$prcfg_name eq ""} {
|
|
|
|
read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
|
|
read_verilog $hdl_files
|
|
read_xdc $xdc_files
|
|
|
|
synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
|
|
write_checkpoint -force $p_prefix.synth.dcp
|
|
close_project
|
|
|
|
} else {
|
|
|
|
create_project -in_memory -part $p_device
|
|
read_verilog $hdl_files
|
|
synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
|
|
write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
|
|
close_project
|
|
}
|
|
}
|
|
|
|
## Run implementation on an partial design; use it in Partial Reconfiguration
|
|
# flow.
|
|
#
|
|
# \param[project_name] - project name
|
|
# \param[prcfg_name] - name of the partial design
|
|
# \param[xdc_files] - XDC constraint source of the partial design
|
|
#
|
|
proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
|
|
|
|
global p_device
|
|
global p_prcfg_init
|
|
global p_prcfg_list
|
|
global p_prcfg_status
|
|
|
|
set p_prefix "$project_name.data/$project_name"
|
|
|
|
if {$prcfg_name eq "default"} {
|
|
set p_prcfg_status 0
|
|
set p_prcfg_list ""
|
|
set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
|
|
file mkdir $project_name.sdk
|
|
}
|
|
|
|
if {$prcfg_name eq "default"} {
|
|
|
|
open_checkpoint $p_prefix.synth.dcp -part $p_device
|
|
read_xdc $xdc_files
|
|
read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
|
|
set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
|
|
opt_design > $p_prefix.${prcfg_name}_opt.rds
|
|
write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
|
|
place_design > $p_prefix.${prcfg_name}_place.rds
|
|
route_design > $p_prefix.${prcfg_name}_route.rds
|
|
|
|
} else {
|
|
|
|
open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
|
|
lock_design -level routing
|
|
read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
|
|
read_xdc $xdc_files
|
|
opt_design > $p_prefix.${prcfg_name}_opt.rds
|
|
place_design > $p_prefix.${prcfg_name}_place.rds
|
|
route_design > $p_prefix.${prcfg_name}_route.rds
|
|
}
|
|
|
|
write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
|
|
report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
|
|
report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
|
|
|
|
if [expr [get_property SLACK [get_timing_paths]] < 0] {
|
|
set p_prcfg_status 1
|
|
puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
|
|
}
|
|
|
|
write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
|
|
update_design -cell i_prcfg -black_box
|
|
write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
|
|
open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
|
|
write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
|
|
write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
|
|
file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
|
|
|
|
if {$prcfg_name ne "default"} {
|
|
lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
|
|
}
|
|
|
|
if {$prcfg_name eq "default"} {
|
|
file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
|
|
}
|
|
}
|
|
|
|
## Verify an implemented partial reconfiguration design, checks if all the
|
|
# partial design are compatible with the base design.
|
|
#
|
|
# \param[project_name] - project name
|
|
#
|
|
proc adi_project_verify {project_name} {
|
|
|
|
# checkpoint for the default design
|
|
global p_prcfg_init
|
|
# list of checkpoints with all the PRs integrated into the default design
|
|
global p_prcfg_list
|
|
global p_prcfg_status
|
|
|
|
set p_prefix "$project_name.data/$project_name"
|
|
|
|
pr_verify -full_check -initial $p_prcfg_init \
|
|
-additional $p_prcfg_list \
|
|
-file $p_prefix.prcfg_verify.log
|
|
|
|
if {$p_prcfg_status == 1} {
|
|
return -code error [format "ERROR: Timing Constraints NOT met!"]
|
|
}
|
|
}
|
|
|